| Message ID | 20241114130340.7354-2-ciprian.hegbeli@analog.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | Add support for ADF4382 | expand |
On 14/11/2024 14:03, Ciprian Hegbeli wrote: > The ADF4382A is a high performance, ultralow jitter, Frac-N PLL > with integrated VCO ideally suited for LO generation for 5G applications > or data converter clock applications. The high performance > PLL has a figure of merit of -239 dBc/Hz, low 1/f Noise and > high PFD frequency of 625MHz in integer mode that can achieve > ultralow in-band noise and integrated jitter. The ADF4382A can > generate frequencies in a fundamental octave range of 11.5 GHz to > 21 GHz, thereby eliminating the need for sub-harmonic filters. The > divide by 2 and 4 output dividers on the part allow frequencies to > be generated from 5.75GHz to 10.5GHz and 2.875GHz to 5.25GHz > respectively. > > Signed-off-by: Ciprian Hegbeli <ciprian.hegbeli@analog.com> > --- > .../bindings/iio/frequency/adi,adf4382.yaml | 141 ++++++++++++++++++ > 1 file changed, 141 insertions(+) > create mode 100644 Documentation/devicetree/bindings/iio/frequency/adi,adf4382.yaml > > diff --git a/Documentation/devicetree/bindings/iio/frequency/adi,adf4382.yaml b/Documentation/devicetree/bindings/iio/frequency/adi,adf4382.yaml > new file mode 100644 > index 000000000000..44a29ac7a2e8 > --- /dev/null > +++ b/Documentation/devicetree/bindings/iio/frequency/adi,adf4382.yaml > @@ -0,0 +1,141 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/iio/frequency/adi,adf4382.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: ADF4382 Microwave Wideband Synthesizer with Integrated VCO > + > +maintainers: > + - Antoniu Miclaus <antoniu.miclaus@analog.com> > + - Ciprian Hegbeli <ciprian.hegbeli@analog.com> > + > +description: The ADF4382 is a high performance, ultralow jitter, Frac-N PLL with > + integrated VCO ideally suited for LO generation for 5G applications > + or data converter clock applications. > + > + https://www.analog.com/en/products/adf4382a.html > + > +properties: > + compatible: > + enum: > + - adi,adf4382 > + - adi,adf4382a > + > + reg: > + maxItems: 1 > + > + spi-max-frequency: > + maximum: 75000000 > + > + clocks: > + description: Clock to provide CLKIN reference clock signal. > + maxItems: 1 > + > + clock-names: > + description: > + External clock that provides reference input frequency. > + items: > + - const: ref_clk > + > + '#clock-cells': > + const: 0 > + > + clock-output-names: > + maxItems: 1 > + > + adi,charge-pump-microamp: > + description: These lines are a bit over 80 chars, maybe you could rearrange them. > + The charge pump current that the external loop filter was designed for. > + If this property is not specified, then the charge pump current is set to the > + default 11100uA. The valid values are listed below. However, if the set value is > + not supported, the driver will look for the closest valid charge pump current. > + anyOf: > + - enum: [790, 990, 1190, 1380, 1590, 1980, 2390, 2790, 3180, 3970, 4770, 5570, 6330, 7910, 9510, 11100] > + > + adi,ref-divider: > + description: > + Input divider of the reference frequency, cannot be lower then 1 or > + higher then 63. > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint32 > + - minimum: 1 > + - maximum: 63 > + - default: 1 > + maxItems: 1 > + > + adi,ref-doubler-enable: > + description: > + Enables the doubling of the reference clock. > + type: boolean > + maxItems: 1 > + > + adi,bleed-word: > + description: > + A small programmable constant charge pump current, known as bleed current, > + can be used to optimize the phase noise and fractional spurious signals > + in fractional mode. > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint32 > + - minimum: 0 > + - maximum: 4095 > + - default: 0 > + maxItems: 1 > + > + adi,power-up-frequency: > + description: > + PLL tunes to the set frequency on probe or defaults to 2,305 GHz. > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint64 > + - minimum: 687500000 > + - maximum: 22000000000 > + - default: 2305000000 > + maxItems: 1 > + > + adi,output-power-value: > + description: > + The output power amplitude level which will be applied for both channels > + at startup. > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint32 > + - minimum: 0 > + - maximum: 15 > + - default: 11 > + maxItems: 1 > + > + adi,spi-3wire-enable: > + description: > + Uses SPI in 3 wire mode, by default is uses 4 wire mode. > + type: boolean > + maxItems: 1 > + > + adi,cmos-3v3: > + description: > + Sets the SPI logic to 3.3V, by defautl it uses 1,8V. > + type: boolean > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + > +additionalProperties: false > + > +examples: > + - | > + spi { > + #address-cells = <1>; > + #size-cells = <0>; > + frequency@0 { > + compatible = "adi,adf4382"; > + reg = <0>; > + spi-max-frequency = <1000000>; > + clocks = <&adf4382_clkin>; > + clock-names = "ref_clk"; Should it not be adi,charge-pump-microamp instead? dt_binding_check complains about this. > + adi,charge-pump-current = <15>; > + adi,ref-divider = <1>; > + }; > + }; > +... Best regards, Javier Carrasco
On 14/11/2024 14:03, Ciprian Hegbeli wrote: > The ADF4382A is a high performance, ultralow jitter, Frac-N PLL > with integrated VCO ideally suited for LO generation for 5G applications > or data converter clock applications. The high performance > PLL has a figure of merit of -239 dBc/Hz, low 1/f Noise and > high PFD frequency of 625MHz in integer mode that can achieve > ultralow in-band noise and integrated jitter. The ADF4382A can > generate frequencies in a fundamental octave range of 11.5 GHz to > 21 GHz, thereby eliminating the need for sub-harmonic filters. The > divide by 2 and 4 output dividers on the part allow frequencies to > be generated from 5.75GHz to 10.5GHz and 2.875GHz to 5.25GHz > respectively. > > Signed-off-by: Ciprian Hegbeli <ciprian.hegbeli@analog.com> > --- ... > + > + adi,cmos-3v3: > + description: A nitpick I overlooked: default. > + Sets the SPI logic to 3.3V, by defautl it uses 1,8V. > + type: boolean > + maxItems: 1 > +
On Thu, 14 Nov 2024 15:03:10 +0200, Ciprian Hegbeli wrote: > The ADF4382A is a high performance, ultralow jitter, Frac-N PLL > with integrated VCO ideally suited for LO generation for 5G applications > or data converter clock applications. The high performance > PLL has a figure of merit of -239 dBc/Hz, low 1/f Noise and > high PFD frequency of 625MHz in integer mode that can achieve > ultralow in-band noise and integrated jitter. The ADF4382A can > generate frequencies in a fundamental octave range of 11.5 GHz to > 21 GHz, thereby eliminating the need for sub-harmonic filters. The > divide by 2 and 4 output dividers on the part allow frequencies to > be generated from 5.75GHz to 10.5GHz and 2.875GHz to 5.25GHz > respectively. > > Signed-off-by: Ciprian Hegbeli <ciprian.hegbeli@analog.com> > --- > .../bindings/iio/frequency/adi,adf4382.yaml | 141 ++++++++++++++++++ > 1 file changed, 141 insertions(+) > create mode 100644 Documentation/devicetree/bindings/iio/frequency/adi,adf4382.yaml > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/iio/frequency/adi,adf4382.example.dtb: frequency@0: 'adi,charge-pump-current' does not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/iio/frequency/adi,adf4382.yaml# doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20241114130340.7354-2-ciprian.hegbeli@analog.com The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
On Thu, Nov 14, 2024 at 03:03:10PM +0200, Ciprian Hegbeli wrote: > The ADF4382A is a high performance, ultralow jitter, Frac-N PLL > with integrated VCO ideally suited for LO generation for 5G applications > or data converter clock applications. The high performance > PLL has a figure of merit of -239 dBc/Hz, low 1/f Noise and > high PFD frequency of 625MHz in integer mode that can achieve > ultralow in-band noise and integrated jitter. The ADF4382A can > generate frequencies in a fundamental octave range of 11.5 GHz to > 21 GHz, thereby eliminating the need for sub-harmonic filters. The > divide by 2 and 4 output dividers on the part allow frequencies to > be generated from 5.75GHz to 10.5GHz and 2.875GHz to 5.25GHz > respectively. > > Signed-off-by: Ciprian Hegbeli <ciprian.hegbeli@analog.com> > --- > .../bindings/iio/frequency/adi,adf4382.yaml | 141 ++++++++++++++++++ > 1 file changed, 141 insertions(+) > create mode 100644 Documentation/devicetree/bindings/iio/frequency/adi,adf4382.yaml > > diff --git a/Documentation/devicetree/bindings/iio/frequency/adi,adf4382.yaml b/Documentation/devicetree/bindings/iio/frequency/adi,adf4382.yaml > new file mode 100644 > index 000000000000..44a29ac7a2e8 > --- /dev/null > +++ b/Documentation/devicetree/bindings/iio/frequency/adi,adf4382.yaml > @@ -0,0 +1,141 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/iio/frequency/adi,adf4382.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: ADF4382 Microwave Wideband Synthesizer with Integrated VCO > + > +maintainers: > + - Antoniu Miclaus <antoniu.miclaus@analog.com> > + - Ciprian Hegbeli <ciprian.hegbeli@analog.com> > + > +description: The ADF4382 is a high performance, ultralow jitter, Frac-N PLL with > + integrated VCO ideally suited for LO generation for 5G applications > + or data converter clock applications. > + > + https://www.analog.com/en/products/adf4382a.html > + > +properties: > + compatible: > + enum: > + - adi,adf4382 > + - adi,adf4382a > + > + reg: > + maxItems: 1 > + > + spi-max-frequency: > + maximum: 75000000 > + > + clocks: > + description: Clock to provide CLKIN reference clock signal. > + maxItems: 1 All you need here is: clocks: items: - description: foo > + > + clock-names: > + description: > + External clock that provides reference input frequency. Drop the description, you have one above. > + items: > + - const: ref_clk > + > + '#clock-cells': > + const: 0 > + > + clock-output-names: > + maxItems: 1 > + > + adi,charge-pump-microamp: > + description: > + The charge pump current that the external loop filter was designed for. > + If this property is not specified, then the charge pump current is set to the > + default 11100uA. The valid values are listed below. However, if the set value is > + not supported, the driver will look for the closest valid charge pump current. > + anyOf: > + - enum: [790, 990, 1190, 1380, 1590, 1980, 2390, 2790, 3180, 3970, 4770, 5570, 6330, 7910, 9510, 11100] Just enum, drop the anyof. > + > + adi,ref-divider: > + description: > + Input divider of the reference frequency, cannot be lower then 1 or > + higher then 63. > + allOf: This allof isn't required, all these can move up a level. Not entirely sure why this is actually required though, shouldn't the driver be able to compute this based on the output frequency requested? > + - $ref: /schemas/types.yaml#/definitions/uint32 > + - minimum: 1 > + - maximum: 63 > + - default: 1 > + maxItems: 1 drop this. > + > + adi,ref-doubler-enable: > + description: > + Enables the doubling of the reference clock. > + type: boolean type: flag but same question here about why this is in the binding. > + maxItems: 1 > + > + adi,bleed-word: > + description: > + A small programmable constant charge pump current, known as bleed current, > + can be used to optimize the phase noise and fractional spurious signals > + in fractional mode. > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint32 > + - minimum: 0 > + - maximum: 4095 > + - default: 0 > + maxItems: 1 Same comments about allOf/maxItems here. Additionally, why is this in the binding, and not something controllable from userspace etc? If it stays in the binding, why "bleed-word" and not "bleed-current-microamps" (or w/e other unit that is more appropriate) > + > + adi,power-up-frequency: > + description: > + PLL tunes to the set frequency on probe or defaults to 2,305 GHz. > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint64 > + - minimum: 687500000 > + - maximum: 22000000000 > + - default: 2305000000 > + maxItems: 1 Same comments here. > + > + adi,output-power-value: > + description: > + The output power amplitude level which will be applied for both channels > + at startup. > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint32 > + - minimum: 0 > + - maximum: 15 > + - default: 11 > + maxItems: 1 Is this a unitless gain or a power that should have a unit? Same comments as other properties about allOf/anyOf. > + > + adi,spi-3wire-enable: spi-3wire is a standard property > + description: > + Uses SPI in 3 wire mode, by default is uses 4 wire mode. > + type: boolean > + maxItems: 1 > + > + adi,cmos-3v3: > + description: > + Sets the SPI logic to 3.3V, by defautl it uses 1,8V. > + type: boolean > + maxItems: 1 type: flag. Drop the maxItems. Cheers, Conor. > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + > +additionalProperties: false > + > +examples: > + - | > + spi { > + #address-cells = <1>; > + #size-cells = <0>; > + frequency@0 { > + compatible = "adi,adf4382"; > + reg = <0>; > + spi-max-frequency = <1000000>; > + clocks = <&adf4382_clkin>; > + clock-names = "ref_clk"; > + adi,charge-pump-current = <15>; > + adi,ref-divider = <1>; > + }; > + }; > +... > -- > 2.43.0 >
On Thu, 14 Nov 2024 15:03:10 +0200 Ciprian Hegbeli <ciprian.hegbeli@analog.com> wrote: Hi Ciprian, > The ADF4382A is a high performance, ultralow jitter, Frac-N PLL > with integrated VCO ideally suited for LO generation for 5G applications > or data converter clock applications. The high performance 5G or data converter clock applications. (no need to say applications twice) > PLL has a figure of merit of -239 dBc/Hz, low 1/f Noise and > high PFD frequency of 625MHz in integer mode that can achieve > ultralow in-band noise and integrated jitter. The ADF4382A can > generate frequencies in a fundamental octave range of 11.5 GHz to > 21 GHz, thereby eliminating the need for sub-harmonic filters. The > divide by 2 and 4 output dividers on the part allow frequencies to > be generated from 5.75GHz to 10.5GHz and 2.875GHz to 5.25GHz > respectively. Wrap this lot to 75 chars otherwise that's fine if more detail than many bother with! :) > > Signed-off-by: Ciprian Hegbeli <ciprian.hegbeli@analog.com> A few additional comments from me inline. > --- > .../bindings/iio/frequency/adi,adf4382.yaml | 141 ++++++++++++++++++ > 1 file changed, 141 insertions(+) > create mode 100644 Documentation/devicetree/bindings/iio/frequency/adi,adf4382.yaml > > diff --git a/Documentation/devicetree/bindings/iio/frequency/adi,adf4382.yaml b/Documentation/devicetree/bindings/iio/frequency/adi,adf4382.yaml > new file mode 100644 > index 000000000000..44a29ac7a2e8 > --- /dev/null > +++ b/Documentation/devicetree/bindings/iio/frequency/adi,adf4382.yaml > @@ -0,0 +1,141 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/iio/frequency/adi,adf4382.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: ADF4382 Microwave Wideband Synthesizer with Integrated VCO > + > +maintainers: > + - Antoniu Miclaus <antoniu.miclaus@analog.com> > + - Ciprian Hegbeli <ciprian.hegbeli@analog.com> > + > +description: The ADF4382 is a high performance, ultralow jitter, Frac-N PLL with > + integrated VCO ideally suited for LO generation for 5G applications > + or data converter clock applications. > + > + https://www.analog.com/en/products/adf4382a.html > + > +properties: > + compatible: > + enum: > + - adi,adf4382 > + - adi,adf4382a Description only talks about the a variant. Why is the one without the a? > + adi,charge-pump-microamp: > + description: > + The charge pump current that the external loop filter was designed for. > + If this property is not specified, then the charge pump current is set to the > + default 11100uA. The valid values are listed below. However, if the set value is > + not supported, the driver will look for the closest valid charge pump current. Don't talk about the driver in a dt-binding. So delete last two sentences. > + anyOf: > + - enum: [790, 990, 1190, 1380, 1590, 1980, 2390, 2790, 3180, 3970, 4770, 5570, 6330, 7910, 9510, 11100] > + > + adi,ref-divider: > + description: > + Input divider of the reference frequency, cannot be lower then 1 or > + higher then 63. Why can this not be derived by the required settings in the driver? That is, why is this a characteristic of the board design? > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint32 > + - minimum: 1 > + - maximum: 63 > + - default: 1 > + maxItems: 1 Don't think the maxItems is needed. > + > + adi,ref-doubler-enable: As above. We should be able to figure out if this is necessary to meet a particular requested output. > + description: > + Enables the doubling of the reference clock. > + type: boolean > + maxItems: 1 > + > + adi,bleed-word: > + description: > + A small programmable constant charge pump current, known as bleed current, > + can be used to optimize the phase noise and fractional spurious signals > + in fractional mode. Can we express this in standard units for current? Also call it bleed-current. > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint32 > + - minimum: 0 > + - maximum: 4095 > + - default: 0 > + maxItems: 1 As above, do we need maxItems? > + > + adi,power-up-frequency: > + description: > + PLL tunes to the set frequency on probe or defaults to 2,305 GHz. > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint64 > + - minimum: 687500000 > + - maximum: 22000000000 > + - default: 2305000000 Why does a default power up frequency make sense? I'd kind of expect the device to not put anything out until software has configured it. > + maxItems: 1 > + > + adi,output-power-value: > + description: > + The output power amplitude level which will be applied for both channels > + at startup. As above. Feels like this should be configured by userspace before anything is enabled. I'd be happy with limits if those make sense (as might reflect what the circuitry can cope with). > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint32 > + - minimum: 0 > + - maximum: 15 > + - default: 11 > + maxItems: 1 > + > + adi,spi-3wire-enable: > + description: > + Uses SPI in 3 wire mode, by default is uses 4 wire mode. Is this standard SPI 3 wire, or an ADI variant? Is spi-3wire from main spi binding appropriate? > + type: boolean > + maxItems: 1 > + > + adi,cmos-3v3: > + description: > + Sets the SPI logic to 3.3V, by defautl it uses 1,8V. spell check. How do you configure it given with the wrong voltage is the SPI bus reliable? > + type: boolean > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names supplies usually required. > + > +additionalProperties: false > + > +examples: > + - | > + spi { > + #address-cells = <1>; > + #size-cells = <0>; > + frequency@0 { Indentation is a bit random. Stick to 4 spaces throughout. > + compatible = "adi,adf4382"; > + reg = <0>; > + spi-max-frequency = <1000000>; > + clocks = <&adf4382_clkin>; > + clock-names = "ref_clk"; > + adi,charge-pump-current = <15>; > + adi,ref-divider = <1>; > + }; > + }; > +...
diff --git a/Documentation/devicetree/bindings/iio/frequency/adi,adf4382.yaml b/Documentation/devicetree/bindings/iio/frequency/adi,adf4382.yaml new file mode 100644 index 000000000000..44a29ac7a2e8 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/frequency/adi,adf4382.yaml @@ -0,0 +1,141 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/frequency/adi,adf4382.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ADF4382 Microwave Wideband Synthesizer with Integrated VCO + +maintainers: + - Antoniu Miclaus <antoniu.miclaus@analog.com> + - Ciprian Hegbeli <ciprian.hegbeli@analog.com> + +description: The ADF4382 is a high performance, ultralow jitter, Frac-N PLL with + integrated VCO ideally suited for LO generation for 5G applications + or data converter clock applications. + + https://www.analog.com/en/products/adf4382a.html + +properties: + compatible: + enum: + - adi,adf4382 + - adi,adf4382a + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 75000000 + + clocks: + description: Clock to provide CLKIN reference clock signal. + maxItems: 1 + + clock-names: + description: + External clock that provides reference input frequency. + items: + - const: ref_clk + + '#clock-cells': + const: 0 + + clock-output-names: + maxItems: 1 + + adi,charge-pump-microamp: + description: + The charge pump current that the external loop filter was designed for. + If this property is not specified, then the charge pump current is set to the + default 11100uA. The valid values are listed below. However, if the set value is + not supported, the driver will look for the closest valid charge pump current. + anyOf: + - enum: [790, 990, 1190, 1380, 1590, 1980, 2390, 2790, 3180, 3970, 4770, 5570, 6330, 7910, 9510, 11100] + + adi,ref-divider: + description: + Input divider of the reference frequency, cannot be lower then 1 or + higher then 63. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 1 + - maximum: 63 + - default: 1 + maxItems: 1 + + adi,ref-doubler-enable: + description: + Enables the doubling of the reference clock. + type: boolean + maxItems: 1 + + adi,bleed-word: + description: + A small programmable constant charge pump current, known as bleed current, + can be used to optimize the phase noise and fractional spurious signals + in fractional mode. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + - maximum: 4095 + - default: 0 + maxItems: 1 + + adi,power-up-frequency: + description: + PLL tunes to the set frequency on probe or defaults to 2,305 GHz. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint64 + - minimum: 687500000 + - maximum: 22000000000 + - default: 2305000000 + maxItems: 1 + + adi,output-power-value: + description: + The output power amplitude level which will be applied for both channels + at startup. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + - maximum: 15 + - default: 11 + maxItems: 1 + + adi,spi-3wire-enable: + description: + Uses SPI in 3 wire mode, by default is uses 4 wire mode. + type: boolean + maxItems: 1 + + adi,cmos-3v3: + description: + Sets the SPI logic to 3.3V, by defautl it uses 1,8V. + type: boolean + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + frequency@0 { + compatible = "adi,adf4382"; + reg = <0>; + spi-max-frequency = <1000000>; + clocks = <&adf4382_clkin>; + clock-names = "ref_clk"; + adi,charge-pump-current = <15>; + adi,ref-divider = <1>; + }; + }; +...
The ADF4382A is a high performance, ultralow jitter, Frac-N PLL with integrated VCO ideally suited for LO generation for 5G applications or data converter clock applications. The high performance PLL has a figure of merit of -239 dBc/Hz, low 1/f Noise and high PFD frequency of 625MHz in integer mode that can achieve ultralow in-band noise and integrated jitter. The ADF4382A can generate frequencies in a fundamental octave range of 11.5 GHz to 21 GHz, thereby eliminating the need for sub-harmonic filters. The divide by 2 and 4 output dividers on the part allow frequencies to be generated from 5.75GHz to 10.5GHz and 2.875GHz to 5.25GHz respectively. Signed-off-by: Ciprian Hegbeli <ciprian.hegbeli@analog.com> --- .../bindings/iio/frequency/adi,adf4382.yaml | 141 ++++++++++++++++++ 1 file changed, 141 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/frequency/adi,adf4382.yaml