| Message ID | 20241118235325.353010-5-vinod.govindapillai@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | drm/i915/xe3: FBC Dirty rect feature support | expand |
On Tue, 19 Nov 2024, Vinod Govindapillai <vinod.govindapillai@intel.com> wrote: > FBC dirty rect support and PSR2 selective fetch canno be enabled > together. In xe3 driver enables the FBC dirty rect feature by > default. So PSR2 is enabled, then mark that plane as FBC cannot > be enabled. Later on we need to find a way to select between > FBC and PSR2 based on amount of damaged areas. > > Bspec: 68881 > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> > --- > drivers/gpu/drm/i915/display/intel_fbc.c | 9 +++++++-- > 1 file changed, 7 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c > index 01080171790f..e1d55f5f2938 100644 > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > @@ -1346,9 +1346,14 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, > * Display 12+ is not supporting FBC with PSR2. > * Recommendation is to keep this combination disabled > * Bspec: 50422 HSD: 14010260002 > + * > + * In Xe3, PSR2 selective fetch and FBC dirty rect feature cannot > + * coexist. So if PSR2 selective fetch is supported then mark that > + * FBC is not supported. > + * TODO: Need a logic to decide between PSR2 and FBC Dirty rect > */ > - if (IS_DISPLAY_VER(display, 12, 14) && crtc_state->has_sel_update && > - !crtc_state->has_panel_replay) { > + if (IS_DISPLAY_VER(display, 12, 14) && DISPLAY_VER(display) >= 30 && This will never be true. BR, Jani. > + crtc_state->has_sel_update && !crtc_state->has_panel_replay) { > plane_state->no_fbc_reason = "PSR2 enabled"; > return 0; > }
On Tue, 2024-11-19 at 10:51 +0200, Jani Nikula wrote: > On Tue, 19 Nov 2024, Vinod Govindapillai <vinod.govindapillai@intel.com> wrote: > > FBC dirty rect support and PSR2 selective fetch canno be enabled > > together. In xe3 driver enables the FBC dirty rect feature by > > default. So PSR2 is enabled, then mark that plane as FBC cannot > > be enabled. Later on we need to find a way to select between > > FBC and PSR2 based on amount of damaged areas. > > > > Bspec: 68881 > > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_fbc.c | 9 +++++++-- > > 1 file changed, 7 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c > > index 01080171790f..e1d55f5f2938 100644 > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > > @@ -1346,9 +1346,14 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, > > * Display 12+ is not supporting FBC with PSR2. > > * Recommendation is to keep this combination disabled > > * Bspec: 50422 HSD: 14010260002 > > + * > > + * In Xe3, PSR2 selective fetch and FBC dirty rect feature cannot > > + * coexist. So if PSR2 selective fetch is supported then mark that > > + * FBC is not supported. > > + * TODO: Need a logic to decide between PSR2 and FBC Dirty rect > > */ > > - if (IS_DISPLAY_VER(display, 12, 14) && crtc_state->has_sel_update && > > - !crtc_state->has_panel_replay) { > > + if (IS_DISPLAY_VER(display, 12, 14) && DISPLAY_VER(display) >= 30 && > > This will never be true. > > BR, > Jani. oops! Thanks! Will fix that! BR vinod > > > + crtc_state->has_sel_update && !crtc_state->has_panel_replay) { > > plane_state->no_fbc_reason = "PSR2 enabled"; > > return 0; > > } >
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 01080171790f..e1d55f5f2938 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -1346,9 +1346,14 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, * Display 12+ is not supporting FBC with PSR2. * Recommendation is to keep this combination disabled * Bspec: 50422 HSD: 14010260002 + * + * In Xe3, PSR2 selective fetch and FBC dirty rect feature cannot + * coexist. So if PSR2 selective fetch is supported then mark that + * FBC is not supported. + * TODO: Need a logic to decide between PSR2 and FBC Dirty rect */ - if (IS_DISPLAY_VER(display, 12, 14) && crtc_state->has_sel_update && - !crtc_state->has_panel_replay) { + if (IS_DISPLAY_VER(display, 12, 14) && DISPLAY_VER(display) >= 30 && + crtc_state->has_sel_update && !crtc_state->has_panel_replay) { plane_state->no_fbc_reason = "PSR2 enabled"; return 0; }
FBC dirty rect support and PSR2 selective fetch canno be enabled together. In xe3 driver enables the FBC dirty rect feature by default. So PSR2 is enabled, then mark that plane as FBC cannot be enabled. Later on we need to find a way to select between FBC and PSR2 based on amount of damaged areas. Bspec: 68881 Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> --- drivers/gpu/drm/i915/display/intel_fbc.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-)