| Message ID | 20241118-pcie-en7581-fixes-v4-5-24bb61703ad7@kernel.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | PCI: mediatek-gen3: mtk_pcie_en7581_power_up() code refactoring | expand |
Quoting Lorenzo Bianconi (2024-11-18 00:04:57) > Airoha EN7581 has a hw bug asserting/releasing PCIE_PE_RSTB signal > causing occasional PCIe link down issues. In order to overcome the > problem, PCIe block is reset using REG_PCI_CONTROL (0x88) and > REG_RESET_CONTROL (0x834) registers available in the clock module > running clk_bulk_prepare_enable in mtk_pcie_en7581_power_up(). > In order to make the code more readable, move the wait for the time > needed to complete the PCIe reset from en7581_pci_enable() to > mtk_pcie_en7581_power_up(). > Reduce reset timeout from 250ms to PCIE_T_PVPERL_MS (100ms). > > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> > --- Acked-by: Stephen Boyd <sboyd@kernel.org>
On Mon, Nov 18, 2024 at 09:04:57AM +0100, Lorenzo Bianconi wrote: > Airoha EN7581 has a hw bug asserting/releasing PCIE_PE_RSTB signal > causing occasional PCIe link down issues. In order to overcome the > problem, PCIe block is reset using REG_PCI_CONTROL (0x88) and > REG_RESET_CONTROL (0x834) registers available in the clock module > running clk_bulk_prepare_enable in mtk_pcie_en7581_power_up(). > In order to make the code more readable, move the wait for the time > needed to complete the PCIe reset from en7581_pci_enable() to > mtk_pcie_en7581_power_up(). > Reduce reset timeout from 250ms to PCIE_T_PVPERL_MS (100ms). > and this reduced timeout has no impact on the behavior? If so, it'd be good to state it explicitly. But this information can be added while applying the patch, so no need to resend just for this. > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> - Mani > --- > drivers/clk/clk-en7523.c | 1 - > drivers/pci/controller/pcie-mediatek-gen3.c | 7 +++++++ > 2 files changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c > index 22fbea61c3dcc05e63f8fa37e203c62b2a6fe79e..bf9d9594bef8a54316e28e56a1642ecb0562377a 100644 > --- a/drivers/clk/clk-en7523.c > +++ b/drivers/clk/clk-en7523.c > @@ -393,7 +393,6 @@ static int en7581_pci_enable(struct clk_hw *hw) > REG_PCI_CONTROL_PERSTOUT; > val = readl(np_base + REG_PCI_CONTROL); > writel(val | mask, np_base + REG_PCI_CONTROL); > - msleep(250); > > return 0; > } > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c > index e4f890a73cb8ada7423301fa7a9acc3e177d0cad..f47c0f2995d94ea99bf41146657bd90b87781a7c 100644 > --- a/drivers/pci/controller/pcie-mediatek-gen3.c > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c > @@ -980,6 +980,13 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) > goto err_clk_prepare_enable; > } > > + /* > + * Airoha EN7581 performs PCIe reset via clk callabacks since it has a > + * hw issue with PCIE_PE_RSTB signal. Add wait for the time needed to > + * complete the PCIe reset. > + */ > + msleep(PCIE_T_PVPERL_MS); > + > return 0; > > err_clk_prepare_enable: > > -- > 2.47.0 >
diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 22fbea61c3dcc05e63f8fa37e203c62b2a6fe79e..bf9d9594bef8a54316e28e56a1642ecb0562377a 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -393,7 +393,6 @@ static int en7581_pci_enable(struct clk_hw *hw) REG_PCI_CONTROL_PERSTOUT; val = readl(np_base + REG_PCI_CONTROL); writel(val | mask, np_base + REG_PCI_CONTROL); - msleep(250); return 0; } diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index e4f890a73cb8ada7423301fa7a9acc3e177d0cad..f47c0f2995d94ea99bf41146657bd90b87781a7c 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -980,6 +980,13 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) goto err_clk_prepare_enable; } + /* + * Airoha EN7581 performs PCIe reset via clk callabacks since it has a + * hw issue with PCIE_PE_RSTB signal. Add wait for the time needed to + * complete the PCIe reset. + */ + msleep(PCIE_T_PVPERL_MS); + return 0; err_clk_prepare_enable: