| Message ID | 20241017114055.13971-2-quic_uaggarwa@quicinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add support to ignore single SE0 glitches | expand |
On Thu, Oct 17, 2024 at 05:10:54PM +0530, Uttkarsh Aggarwal wrote: > Adding a new 'snps,filter-se0-fsls-eop quirk' DT quirk to dwc3 core to set > GUCTL1 BIT 29. When set, controller will ignore single SE0 glitch on the > linestate during transmission. Only two or more SE0 is considered as > valid EOP on FS/LS port. This bit is applicable only in FS in device mode > and FS/LS mode of operation in host mode. Why this is not device/compatible specific? Just like all other quirks pushed last one year. > > Signed-off-by: Uttkarsh Aggarwal <quic_uaggarwa@quicinc.com> > --- > Documentation/devicetree/bindings/usb/snps,dwc3.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml > index 1cd0ca90127d..d9e813bbcd80 100644 > --- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml > +++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml > @@ -180,6 +180,12 @@ properties: > description: When set core will set Tx de-emphasis value > type: boolean > > + snps,filter-se0-fsls-eop-quirk: > + description: > + When set controller will ignore single SE0 glitch on the linestate during transmit Does not look like wrapped according to coding style (checkpatch is not a coding style document). Best regards, Krzysztof
On 10/18/2024 11:57 AM, Krzysztof Kozlowski wrote: > On Thu, Oct 17, 2024 at 05:10:54PM +0530, Uttkarsh Aggarwal wrote: >> Adding a new 'snps,filter-se0-fsls-eop quirk' DT quirk to dwc3 core to set >> GUCTL1 BIT 29. When set, controller will ignore single SE0 glitch on the >> linestate during transmission. Only two or more SE0 is considered as >> valid EOP on FS/LS port. This bit is applicable only in FS in device mode >> and FS/LS mode of operation in host mode. > > Why this is not device/compatible specific? Just like all other quirks > pushed last one year. Hi Krzysztof, Apologies for a late reply from our end. In DWC3 core/dwc3-qcom atleast, there have been no compatible specific quirks added. Also since this is a property of the Synopsys controller hardware and not QC specific one, can we add it in bindings itself. Because this is a property other vendors might also use and adding it via compatible might not be appropriate. Let us know your thoughts on this. Regards, Krishna, > >> >> Signed-off-by: Uttkarsh Aggarwal <quic_uaggarwa@quicinc.com> >> --- >> Documentation/devicetree/bindings/usb/snps,dwc3.yaml | 6 ++++++ >> 1 file changed, 6 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml >> index 1cd0ca90127d..d9e813bbcd80 100644 >> --- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml >> +++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml >> @@ -180,6 +180,12 @@ properties: >> description: When set core will set Tx de-emphasis value >> type: boolean >> >> + snps,filter-se0-fsls-eop-quirk: >> + description: >> + When set controller will ignore single SE0 glitch on the linestate during transmit > > Does not look like wrapped according to coding style (checkpatch is not > a coding style document). > > Best regards, > Krzysztof > >
On 07/11/2024 07:17, Krishna Kurapati wrote: > > > On 10/18/2024 11:57 AM, Krzysztof Kozlowski wrote: >> On Thu, Oct 17, 2024 at 05:10:54PM +0530, Uttkarsh Aggarwal wrote: >>> Adding a new 'snps,filter-se0-fsls-eop quirk' DT quirk to dwc3 core to set >>> GUCTL1 BIT 29. When set, controller will ignore single SE0 glitch on the >>> linestate during transmission. Only two or more SE0 is considered as >>> valid EOP on FS/LS port. This bit is applicable only in FS in device mode >>> and FS/LS mode of operation in host mode. >> >> Why this is not device/compatible specific? Just like all other quirks >> pushed last one year. > > Hi Krzysztof, > > Apologies for a late reply from our end. > > In DWC3 core/dwc3-qcom atleast, there have been no compatible specific > quirks added. Nothing stops from adding these, I think. > Also since this is a property of the Synopsys controller > hardware and not QC specific one, can we add it in bindings itself. > Because this is a property other vendors might also use and adding it > via compatible might not be appropriate. This does no answer my question. I don't see how this is not related to one specific piece of SoC. If you claim this is board-related, not SoC, give some arguments. Repeating the same is just no helping. Best regards, Krzysztof
On 11/7/2024 3:25 PM, Krzysztof Kozlowski wrote: > On 07/11/2024 07:17, Krishna Kurapati wrote: >> >> >> On 10/18/2024 11:57 AM, Krzysztof Kozlowski wrote: >>> On Thu, Oct 17, 2024 at 05:10:54PM +0530, Uttkarsh Aggarwal wrote: >>>> Adding a new 'snps,filter-se0-fsls-eop quirk' DT quirk to dwc3 core to set >>>> GUCTL1 BIT 29. When set, controller will ignore single SE0 glitch on the >>>> linestate during transmission. Only two or more SE0 is considered as >>>> valid EOP on FS/LS port. This bit is applicable only in FS in device mode >>>> and FS/LS mode of operation in host mode. >>> >>> Why this is not device/compatible specific? Just like all other quirks >>> pushed last one year. >> >> Hi Krzysztof, >> >> Apologies for a late reply from our end. >> >> In DWC3 core/dwc3-qcom atleast, there have been no compatible specific >> quirks added. > Sorry again for late reply. > Nothing stops from adding these, I think. > Agree, we can take that approach of adding soc specific compatibles to dwc3 driver instead of adding through bindings. >> Also since this is a property of the Synopsys controller >> hardware and not QC specific one, can we add it in bindings itself. >> Because this is a property other vendors might also use and adding it >> via compatible might not be appropriate. > > This does no answer my question. I don't see how this is not related to > one specific piece of SoC. > > If you claim this is board-related, not SoC, give some arguments. > Repeating the same is just no helping. > But my point was that although the issue was found only on some QC SoC's, the solution still lies in some bits being set in controller register space and it is part of Synopsys IP. So wouldn't officially we add that support in bindings and then enable/disable the feature via DT like we did for other quirks ? If many SoC's need it in future, the driver needs to add a long list of compatible specific data which otherwise might be quirks in DT. Regards, Krishna,
diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml index 1cd0ca90127d..d9e813bbcd80 100644 --- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml @@ -180,6 +180,12 @@ properties: description: When set core will set Tx de-emphasis value type: boolean + snps,filter-se0-fsls-eop-quirk: + description: + When set controller will ignore single SE0 glitch on the linestate during transmit + Only two or more SE0 is considered as a valid EOP on FS/LS port. + type: boolean + snps,tx_de_emphasis: description: The value driven to the PHY is controlled by the LTSSM during USB3
Adding a new 'snps,filter-se0-fsls-eop quirk' DT quirk to dwc3 core to set GUCTL1 BIT 29. When set, controller will ignore single SE0 glitch on the linestate during transmission. Only two or more SE0 is considered as valid EOP on FS/LS port. This bit is applicable only in FS in device mode and FS/LS mode of operation in host mode. Signed-off-by: Uttkarsh Aggarwal <quic_uaggarwa@quicinc.com> --- Documentation/devicetree/bindings/usb/snps,dwc3.yaml | 6 ++++++ 1 file changed, 6 insertions(+)