| Message ID | 20241119104521.575377-8-arun.r.murthy@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Display Global Histogram | expand |
> -----Original Message----- > From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Arun R > Murthy > Sent: Tuesday, November 19, 2024 4:15 PM > To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; dri- > devel@lists.freedesktop.org > Cc: Murthy, Arun R <arun.r.murthy@intel.com> > Subject: [PATCHv4 7/8] drm/i915/histogram: Histogram changes for Display > 20+ > > In Display 20+, new registers are added for setting index, reading histogram > and writing the IET. Bspec reference for new registers being added please > > v2: Removed duplicate code (Jani) > v3: Moved histogram core changes to earlier patches (Jani/Suraj) > v4: Rebased after addressing comments on patch 1 > > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com> > --- > .../gpu/drm/i915/display/intel_histogram.c | 111 +++++++++++++----- > .../drm/i915/display/intel_histogram_regs.h | 25 ++++ > 2 files changed, 105 insertions(+), 31 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_histogram.c > b/drivers/gpu/drm/i915/display/intel_histogram.c > index fdcc64677e96..beaad9256e01 100644 > --- a/drivers/gpu/drm/i915/display/intel_histogram.c > +++ b/drivers/gpu/drm/i915/display/intel_histogram.c > @@ -29,6 +29,51 @@ struct intel_histogram { > u32 bin_data[HISTOGRAM_BIN_COUNT]; > }; > > +static void set_bin_index_0(struct intel_display *display, enum pipe > +pipe) { > + if (DISPLAY_VER(display) >= 20) > + intel_de_rmw(display, DPST_IE_INDEX(pipe), > + DPST_IE_BIN_INDEX_MASK, > DPST_IE_BIN_INDEX(0)); > + else > + intel_de_rmw(display, DPST_CTL(pipe), > + DPST_CTL_BIN_REG_FUNC_SEL | > DPST_CTL_BIN_REG_MASK, > + DPST_CTL_BIN_REG_FUNC_IE | > DPST_CTL_BIN_REG_CLEAR); } > + > +static void write_iet(struct intel_display *display, enum pipe pipe, > + u32 *data) > +{ > + int i; > + > + if (DISPLAY_VER(display) >= 20) { > + for (i = 0; i < HISTOGRAM_IET_LENGTH; i++) { > + intel_de_rmw(display, DPST_IE_BIN(pipe), > + DPST_IE_BIN_DATA_MASK, > + DPST_IE_BIN_DATA(data[i])); > + drm_dbg_atomic(display->drm, "iet_lut[%d]=%x\n", > + i, data[i]); > + } > + } else { > + for (i = 0; i < HISTOGRAM_IET_LENGTH; i++) { > + intel_de_rmw(display, DPST_BIN(pipe), > + DPST_BIN_DATA_MASK, data[i]); > + drm_dbg_atomic(display->drm, "iet_lut[%d]=%x\n", > + i, data[i]); > + } > + } > +} The above code can be configured as shown below int i; int register_base, data_mask; if (DISPLAY_VER(display) >= 20) { register_base = DPST_IE_BIN(pipe); data_mask = DPST_IE_BIN_DATA_MASK; } else { register_base = DPST_BIN(pipe); data_mask = DPST_BIN_DATA_MASK; } for (i = 0; i < HISTOGRAM_IET_LENGTH; i++) { intel_de_rmw(display, register_base, data_mask, data[i]); drm_dbg_atomic(display->drm, "iet_lut[%d]=%x\n", i, data[i]); } Regards, Suraj Kandpal > + > +static void set_histogram_index_0(struct intel_display *display, enum > +pipe pipe) { > + if (DISPLAY_VER(display) >= 20) > + intel_de_rmw(display, DPST_HIST_INDEX(pipe), > + DPST_HIST_BIN_INDEX_MASK, > + DPST_HIST_BIN_INDEX(0)); > + else > + intel_de_rmw(display, DPST_CTL(pipe), > + DPST_CTL_BIN_REG_FUNC_SEL | > DPST_CTL_BIN_REG_MASK, 0); } > + > static bool intel_histogram_get_data(struct intel_crtc *intel_crtc) { > struct intel_display *display = to_intel_display(intel_crtc); @@ -40,9 > +85,13 @@ static bool intel_histogram_get_data(struct intel_crtc *intel_crtc) > retry_count = 0; > > while (index < HISTOGRAM_BIN_COUNT) { > - dpstbin = intel_de_read(display, DPST_BIN(intel_crtc->pipe)); > + dpstbin = intel_de_read(display, (DISPLAY_VER(display) >= 20 > ? > + DPST_HIST_BIN(intel_crtc->pipe) : > + DPST_BIN(intel_crtc->pipe))); > if (!(dpstbin & DPST_BIN_BUSY)) { > - histogram->bin_data[index] = dpstbin & > DPST_BIN_DATA_MASK; > + histogram->bin_data[index] = dpstbin & > (DISPLAY_VER(display) >= 20 ? > + > DPST_HIST_BIN_DATA_MASK : > + > DPST_BIN_DATA_MASK); > index++; > } else { > /* > @@ -58,9 +107,7 @@ static bool intel_histogram_get_data(struct intel_crtc > *intel_crtc) > /* Add a delay before retrying */ > fsleep(HISTOGRAM_BIN_READ_DELAY); > index = 0; > - intel_de_rmw(display, DPST_CTL(intel_crtc->pipe), > - DPST_CTL_BIN_REG_FUNC_SEL | > - DPST_CTL_BIN_REG_MASK, 0); > + set_histogram_index_0(display, intel_crtc->pipe); > } > } > return true; > @@ -84,8 +131,8 @@ static void intel_histogram_handle_int_work(struct > work_struct *work) > * Set DPST_CTL Bin Reg function select to TC > * Set DPST_CTL Bin Register Index to 0 > */ > - intel_de_rmw(display, DPST_CTL(intel_crtc->pipe), > - DPST_CTL_BIN_REG_FUNC_SEL | > DPST_CTL_BIN_REG_MASK, 0); > + set_histogram_index_0(display, intel_crtc->pipe); > + > if (intel_histogram_get_data(intel_crtc)) { > drm_property_replace_global_blob(display->drm, > &intel_crtc->config->histogram.histogram, > @@ -158,13 +205,20 @@ static int intel_histogram_enable(struct intel_crtc > *intel_crtc) > if (histogram->enable) > return 0; > > - /* enable histogram, clear DPST_BIN reg and select TC function */ > - intel_de_rmw(display, DPST_CTL(pipe), > - DPST_CTL_BIN_REG_FUNC_SEL | DPST_CTL_IE_HIST_EN | > - DPST_CTL_HIST_MODE | > DPST_CTL_IE_TABLE_VALUE_FORMAT, > - DPST_CTL_BIN_REG_FUNC_TC | DPST_CTL_IE_HIST_EN | > - DPST_CTL_HIST_MODE_HSV | > - DPST_CTL_IE_TABLE_VALUE_FORMAT_1INT_9FRAC); > + if (DISPLAY_VER(display) >= 20) > + intel_de_rmw(display, DPST_CTL(pipe), > + DPST_CTL_IE_HIST_EN | > + DPST_CTL_HIST_MODE, > + DPST_CTL_IE_HIST_EN | > + DPST_CTL_HIST_MODE_HSV); > + else > + /* enable histogram, clear DPST_BIN reg and select TC > function */ > + intel_de_rmw(display, DPST_CTL(pipe), > + DPST_CTL_BIN_REG_FUNC_SEL | > DPST_CTL_IE_HIST_EN | > + DPST_CTL_HIST_MODE | > DPST_CTL_IE_TABLE_VALUE_FORMAT, > + DPST_CTL_BIN_REG_FUNC_TC | > DPST_CTL_IE_HIST_EN | > + DPST_CTL_HIST_MODE_HSV | > + > DPST_CTL_IE_TABLE_VALUE_FORMAT_1INT_9FRAC); > > /* Re-Visit: check if wait for one vblank is required */ > drm_crtc_wait_one_vblank(&intel_crtc->base); > @@ -236,7 +290,6 @@ int intel_histogram_set_iet_lut(struct intel_crtc > *intel_crtc, u32 *data) > struct intel_histogram *histogram = intel_crtc->histogram; > struct intel_display *display = to_intel_display(intel_crtc); > int pipe = intel_crtc->pipe; > - int i = 0; > > if (!histogram) > return -EINVAL; > @@ -261,24 +314,20 @@ int intel_histogram_set_iet_lut(struct intel_crtc > *intel_crtc, u32 *data) > * Set DPST_CTL Bin Reg function select to IE > * Set DPST_CTL Bin Register Index to 0 > */ > - intel_de_rmw(display, DPST_CTL(pipe), > - DPST_CTL_BIN_REG_FUNC_SEL | > DPST_CTL_BIN_REG_MASK, > - DPST_CTL_BIN_REG_FUNC_IE | > DPST_CTL_BIN_REG_CLEAR); > - > - for (i = 0; i < HISTOGRAM_IET_LENGTH; i++) { > - intel_de_rmw(display, DPST_BIN(pipe), > - DPST_BIN_DATA_MASK, data[i]); > - drm_dbg_atomic(display->drm, "iet_lut[%d]=%x\n", i, > data[i]); > + set_bin_index_0(display, pipe); > + write_iet(display, pipe, data); > + if (DISPLAY_VER(display) < 20) { > + intel_de_rmw(display, DPST_CTL(pipe), > + DPST_CTL_ENHANCEMENT_MODE_MASK | > + DPST_CTL_IE_MODI_TABLE_EN, > + DPST_CTL_EN_MULTIPLICATIVE | > + DPST_CTL_IE_MODI_TABLE_EN); > + /* Once IE is applied, change DPST CTL to TC */ > + intel_de_rmw(display, DPST_CTL(pipe), > + DPST_CTL_BIN_REG_FUNC_SEL, > + DPST_CTL_BIN_REG_FUNC_TC); > } > > - intel_de_rmw(display, DPST_CTL(pipe), > - DPST_CTL_ENHANCEMENT_MODE_MASK | > DPST_CTL_IE_MODI_TABLE_EN, > - DPST_CTL_EN_MULTIPLICATIVE | > DPST_CTL_IE_MODI_TABLE_EN); > - > - /* Once IE is applied, change DPST CTL to TC */ > - intel_de_rmw(display, DPST_CTL(pipe), > - DPST_CTL_BIN_REG_FUNC_SEL, > DPST_CTL_BIN_REG_FUNC_TC); > - > return 0; > } > > diff --git a/drivers/gpu/drm/i915/display/intel_histogram_regs.h > b/drivers/gpu/drm/i915/display/intel_histogram_regs.h > index e50b1448bd40..2a52ac9282c1 100644 > --- a/drivers/gpu/drm/i915/display/intel_histogram_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_histogram_regs.h > @@ -44,6 +44,31 @@ > #define _DPST_BIN_B 0x491C4 > #define DPST_BIN(pipe) > _MMIO_PIPE(pipe, _DPST_BIN_A, _DPST_BIN_B) > #define DPST_BIN_DATA_MASK > REG_GENMASK(23, 0) > +#define DPST_BIN_DATA > REG_FIELD_PREP(DPST_BIN_DATA_MASK, val) > #define DPST_BIN_BUSY REG_BIT(31) > > +#define _DPST_HIST_INDEX_A 0x490D8 > +#define _DPST_HIST_INDEX_B 0x491D8 > +#define DPST_HIST_INDEX(pipe) > _MMIO_PIPE(pipe, _DPST_HIST_INDEX_A, _DPST_HIST_INDEX_B) > +#define DPST_HIST_BIN_INDEX_MASK > REG_GENMASK(4, 0) > +#define DPST_HIST_BIN_INDEX(val) > REG_FIELD_PREP(DPST_HIST_BIN_INDEX_MASK, val) > + > +#define _DPST_HIST_BIN_A 0x490C4 > +#define _DPST_HIST_BIN_B 0x491C4 > +#define DPST_HIST_BIN(pipe) _MMIO_PIPE(pipe, > _DPST_HIST_BIN_A, _DPST_HIST_BIN_B) > +#define DPST_HIST_BIN_BUSY REG_BIT(31) > +#define DPST_HIST_BIN_DATA_MASK > REG_GENMASK(30, 0) > + > +#define _DPST_IE_BIN_A 0x490CC > +#define _DPST_IE_BIN_B 0x491CC > +#define DPST_IE_BIN(pipe) _MMIO_PIPE(pipe, > _DPST_IE_BIN_A, _DPST_IE_BIN_B) > +#define DPST_IE_BIN_DATA_MASK > REG_GENMASK(9, 0) > +#define DPST_IE_BIN_DATA(val) > REG_FIELD_PREP(DPST_IE_BIN_DATA_MASK, val) > + > +#define _DPST_IE_INDEX_A 0x490DC > +#define _DPST_IE_INDEX_B 0x491DC > +#define DPST_IE_INDEX(pipe) _MMIO_PIPE(pipe, > _DPST_IE_INDEX_A, _DPST_IE_INDEX_B) > +#define DPST_IE_BIN_INDEX_MASK > REG_GENMASK(6, 0) > +#define DPST_IE_BIN_INDEX(val) > REG_FIELD_PREP(DPST_IE_BIN_INDEX_MASK, val) > + > #endif /* __INTEL_HISTOGRAM_REGS_H__ */ > -- > 2.25.1
> -----Original Message----- > From: Kandpal, Suraj <suraj.kandpal@intel.com> > Sent: Wednesday, November 20, 2024 3:55 PM > To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-xe@lists.freedesktop.org; > intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org > Cc: Murthy, Arun R <arun.r.murthy@intel.com> > Subject: RE: [PATCHv4 7/8] drm/i915/histogram: Histogram changes for Display > 20+ > > > > > -----Original Message----- > > From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of > > Arun R Murthy > > Sent: Tuesday, November 19, 2024 4:15 PM > > To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; > > dri- devel@lists.freedesktop.org > > Cc: Murthy, Arun R <arun.r.murthy@intel.com> > > Subject: [PATCHv4 7/8] drm/i915/histogram: Histogram changes for > > Display > > 20+ > > > > In Display 20+, new registers are added for setting index, reading > > histogram and writing the IET. > > Bspec reference for new registers being added please > > > > > v2: Removed duplicate code (Jani) > > v3: Moved histogram core changes to earlier patches (Jani/Suraj) > > v4: Rebased after addressing comments on patch 1 > > > > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com> > > --- > > .../gpu/drm/i915/display/intel_histogram.c | 111 +++++++++++++----- > > .../drm/i915/display/intel_histogram_regs.h | 25 ++++ > > 2 files changed, 105 insertions(+), 31 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_histogram.c > > b/drivers/gpu/drm/i915/display/intel_histogram.c > > index fdcc64677e96..beaad9256e01 100644 > > --- a/drivers/gpu/drm/i915/display/intel_histogram.c > > +++ b/drivers/gpu/drm/i915/display/intel_histogram.c > > @@ -29,6 +29,51 @@ struct intel_histogram { > > u32 bin_data[HISTOGRAM_BIN_COUNT]; > > }; > > > > +static void set_bin_index_0(struct intel_display *display, enum pipe > > +pipe) { > > + if (DISPLAY_VER(display) >= 20) > > + intel_de_rmw(display, DPST_IE_INDEX(pipe), > > + DPST_IE_BIN_INDEX_MASK, > > DPST_IE_BIN_INDEX(0)); > > + else > > + intel_de_rmw(display, DPST_CTL(pipe), > > + DPST_CTL_BIN_REG_FUNC_SEL | > > DPST_CTL_BIN_REG_MASK, > > + DPST_CTL_BIN_REG_FUNC_IE | > > DPST_CTL_BIN_REG_CLEAR); } > > + > > +static void write_iet(struct intel_display *display, enum pipe pipe, > > + u32 *data) > > +{ > > + int i; > > + > > + if (DISPLAY_VER(display) >= 20) { > > + for (i = 0; i < HISTOGRAM_IET_LENGTH; i++) { > > + intel_de_rmw(display, DPST_IE_BIN(pipe), > > + DPST_IE_BIN_DATA_MASK, > > + DPST_IE_BIN_DATA(data[i])); > > + drm_dbg_atomic(display->drm, "iet_lut[%d]=%x\n", > > + i, data[i]); > > + } > > + } else { > > + for (i = 0; i < HISTOGRAM_IET_LENGTH; i++) { > > + intel_de_rmw(display, DPST_BIN(pipe), > > + DPST_BIN_DATA_MASK, data[i]); > > + drm_dbg_atomic(display->drm, "iet_lut[%d]=%x\n", > > + i, data[i]); > > + } > > + } > > +} > > The above code can be configured as shown below > > int i; > int register_base, data_mask; > > if (DISPLAY_VER(display) >= 20) { > register_base = DPST_IE_BIN(pipe); > data_mask = DPST_IE_BIN_DATA_MASK; > } else { > register_base = DPST_BIN(pipe); > data_mask = DPST_BIN_DATA_MASK; > } > > for (i = 0; i < HISTOGRAM_IET_LENGTH; i++) { > intel_de_rmw(display, register_base, data_mask, data[i]); > drm_dbg_atomic(display->drm, "iet_lut[%d]=%x\n", i, data[i]); } > Writing the data[i] to be writing to the reg bit config also varies. So rewriting this code within the for loop to optimize the code. Thanks and Regards, Arun R Murthy -------------------
diff --git a/drivers/gpu/drm/i915/display/intel_histogram.c b/drivers/gpu/drm/i915/display/intel_histogram.c index fdcc64677e96..beaad9256e01 100644 --- a/drivers/gpu/drm/i915/display/intel_histogram.c +++ b/drivers/gpu/drm/i915/display/intel_histogram.c @@ -29,6 +29,51 @@ struct intel_histogram { u32 bin_data[HISTOGRAM_BIN_COUNT]; }; +static void set_bin_index_0(struct intel_display *display, enum pipe pipe) +{ + if (DISPLAY_VER(display) >= 20) + intel_de_rmw(display, DPST_IE_INDEX(pipe), + DPST_IE_BIN_INDEX_MASK, DPST_IE_BIN_INDEX(0)); + else + intel_de_rmw(display, DPST_CTL(pipe), + DPST_CTL_BIN_REG_FUNC_SEL | DPST_CTL_BIN_REG_MASK, + DPST_CTL_BIN_REG_FUNC_IE | DPST_CTL_BIN_REG_CLEAR); +} + +static void write_iet(struct intel_display *display, enum pipe pipe, + u32 *data) +{ + int i; + + if (DISPLAY_VER(display) >= 20) { + for (i = 0; i < HISTOGRAM_IET_LENGTH; i++) { + intel_de_rmw(display, DPST_IE_BIN(pipe), + DPST_IE_BIN_DATA_MASK, + DPST_IE_BIN_DATA(data[i])); + drm_dbg_atomic(display->drm, "iet_lut[%d]=%x\n", + i, data[i]); + } + } else { + for (i = 0; i < HISTOGRAM_IET_LENGTH; i++) { + intel_de_rmw(display, DPST_BIN(pipe), + DPST_BIN_DATA_MASK, data[i]); + drm_dbg_atomic(display->drm, "iet_lut[%d]=%x\n", + i, data[i]); + } + } +} + +static void set_histogram_index_0(struct intel_display *display, enum pipe pipe) +{ + if (DISPLAY_VER(display) >= 20) + intel_de_rmw(display, DPST_HIST_INDEX(pipe), + DPST_HIST_BIN_INDEX_MASK, + DPST_HIST_BIN_INDEX(0)); + else + intel_de_rmw(display, DPST_CTL(pipe), + DPST_CTL_BIN_REG_FUNC_SEL | DPST_CTL_BIN_REG_MASK, 0); +} + static bool intel_histogram_get_data(struct intel_crtc *intel_crtc) { struct intel_display *display = to_intel_display(intel_crtc); @@ -40,9 +85,13 @@ static bool intel_histogram_get_data(struct intel_crtc *intel_crtc) retry_count = 0; while (index < HISTOGRAM_BIN_COUNT) { - dpstbin = intel_de_read(display, DPST_BIN(intel_crtc->pipe)); + dpstbin = intel_de_read(display, (DISPLAY_VER(display) >= 20 ? + DPST_HIST_BIN(intel_crtc->pipe) : + DPST_BIN(intel_crtc->pipe))); if (!(dpstbin & DPST_BIN_BUSY)) { - histogram->bin_data[index] = dpstbin & DPST_BIN_DATA_MASK; + histogram->bin_data[index] = dpstbin & (DISPLAY_VER(display) >= 20 ? + DPST_HIST_BIN_DATA_MASK : + DPST_BIN_DATA_MASK); index++; } else { /* @@ -58,9 +107,7 @@ static bool intel_histogram_get_data(struct intel_crtc *intel_crtc) /* Add a delay before retrying */ fsleep(HISTOGRAM_BIN_READ_DELAY); index = 0; - intel_de_rmw(display, DPST_CTL(intel_crtc->pipe), - DPST_CTL_BIN_REG_FUNC_SEL | - DPST_CTL_BIN_REG_MASK, 0); + set_histogram_index_0(display, intel_crtc->pipe); } } return true; @@ -84,8 +131,8 @@ static void intel_histogram_handle_int_work(struct work_struct *work) * Set DPST_CTL Bin Reg function select to TC * Set DPST_CTL Bin Register Index to 0 */ - intel_de_rmw(display, DPST_CTL(intel_crtc->pipe), - DPST_CTL_BIN_REG_FUNC_SEL | DPST_CTL_BIN_REG_MASK, 0); + set_histogram_index_0(display, intel_crtc->pipe); + if (intel_histogram_get_data(intel_crtc)) { drm_property_replace_global_blob(display->drm, &intel_crtc->config->histogram.histogram, @@ -158,13 +205,20 @@ static int intel_histogram_enable(struct intel_crtc *intel_crtc) if (histogram->enable) return 0; - /* enable histogram, clear DPST_BIN reg and select TC function */ - intel_de_rmw(display, DPST_CTL(pipe), - DPST_CTL_BIN_REG_FUNC_SEL | DPST_CTL_IE_HIST_EN | - DPST_CTL_HIST_MODE | DPST_CTL_IE_TABLE_VALUE_FORMAT, - DPST_CTL_BIN_REG_FUNC_TC | DPST_CTL_IE_HIST_EN | - DPST_CTL_HIST_MODE_HSV | - DPST_CTL_IE_TABLE_VALUE_FORMAT_1INT_9FRAC); + if (DISPLAY_VER(display) >= 20) + intel_de_rmw(display, DPST_CTL(pipe), + DPST_CTL_IE_HIST_EN | + DPST_CTL_HIST_MODE, + DPST_CTL_IE_HIST_EN | + DPST_CTL_HIST_MODE_HSV); + else + /* enable histogram, clear DPST_BIN reg and select TC function */ + intel_de_rmw(display, DPST_CTL(pipe), + DPST_CTL_BIN_REG_FUNC_SEL | DPST_CTL_IE_HIST_EN | + DPST_CTL_HIST_MODE | DPST_CTL_IE_TABLE_VALUE_FORMAT, + DPST_CTL_BIN_REG_FUNC_TC | DPST_CTL_IE_HIST_EN | + DPST_CTL_HIST_MODE_HSV | + DPST_CTL_IE_TABLE_VALUE_FORMAT_1INT_9FRAC); /* Re-Visit: check if wait for one vblank is required */ drm_crtc_wait_one_vblank(&intel_crtc->base); @@ -236,7 +290,6 @@ int intel_histogram_set_iet_lut(struct intel_crtc *intel_crtc, u32 *data) struct intel_histogram *histogram = intel_crtc->histogram; struct intel_display *display = to_intel_display(intel_crtc); int pipe = intel_crtc->pipe; - int i = 0; if (!histogram) return -EINVAL; @@ -261,24 +314,20 @@ int intel_histogram_set_iet_lut(struct intel_crtc *intel_crtc, u32 *data) * Set DPST_CTL Bin Reg function select to IE * Set DPST_CTL Bin Register Index to 0 */ - intel_de_rmw(display, DPST_CTL(pipe), - DPST_CTL_BIN_REG_FUNC_SEL | DPST_CTL_BIN_REG_MASK, - DPST_CTL_BIN_REG_FUNC_IE | DPST_CTL_BIN_REG_CLEAR); - - for (i = 0; i < HISTOGRAM_IET_LENGTH; i++) { - intel_de_rmw(display, DPST_BIN(pipe), - DPST_BIN_DATA_MASK, data[i]); - drm_dbg_atomic(display->drm, "iet_lut[%d]=%x\n", i, data[i]); + set_bin_index_0(display, pipe); + write_iet(display, pipe, data); + if (DISPLAY_VER(display) < 20) { + intel_de_rmw(display, DPST_CTL(pipe), + DPST_CTL_ENHANCEMENT_MODE_MASK | + DPST_CTL_IE_MODI_TABLE_EN, + DPST_CTL_EN_MULTIPLICATIVE | + DPST_CTL_IE_MODI_TABLE_EN); + /* Once IE is applied, change DPST CTL to TC */ + intel_de_rmw(display, DPST_CTL(pipe), + DPST_CTL_BIN_REG_FUNC_SEL, + DPST_CTL_BIN_REG_FUNC_TC); } - intel_de_rmw(display, DPST_CTL(pipe), - DPST_CTL_ENHANCEMENT_MODE_MASK | DPST_CTL_IE_MODI_TABLE_EN, - DPST_CTL_EN_MULTIPLICATIVE | DPST_CTL_IE_MODI_TABLE_EN); - - /* Once IE is applied, change DPST CTL to TC */ - intel_de_rmw(display, DPST_CTL(pipe), - DPST_CTL_BIN_REG_FUNC_SEL, DPST_CTL_BIN_REG_FUNC_TC); - return 0; } diff --git a/drivers/gpu/drm/i915/display/intel_histogram_regs.h b/drivers/gpu/drm/i915/display/intel_histogram_regs.h index e50b1448bd40..2a52ac9282c1 100644 --- a/drivers/gpu/drm/i915/display/intel_histogram_regs.h +++ b/drivers/gpu/drm/i915/display/intel_histogram_regs.h @@ -44,6 +44,31 @@ #define _DPST_BIN_B 0x491C4 #define DPST_BIN(pipe) _MMIO_PIPE(pipe, _DPST_BIN_A, _DPST_BIN_B) #define DPST_BIN_DATA_MASK REG_GENMASK(23, 0) +#define DPST_BIN_DATA REG_FIELD_PREP(DPST_BIN_DATA_MASK, val) #define DPST_BIN_BUSY REG_BIT(31) +#define _DPST_HIST_INDEX_A 0x490D8 +#define _DPST_HIST_INDEX_B 0x491D8 +#define DPST_HIST_INDEX(pipe) _MMIO_PIPE(pipe, _DPST_HIST_INDEX_A, _DPST_HIST_INDEX_B) +#define DPST_HIST_BIN_INDEX_MASK REG_GENMASK(4, 0) +#define DPST_HIST_BIN_INDEX(val) REG_FIELD_PREP(DPST_HIST_BIN_INDEX_MASK, val) + +#define _DPST_HIST_BIN_A 0x490C4 +#define _DPST_HIST_BIN_B 0x491C4 +#define DPST_HIST_BIN(pipe) _MMIO_PIPE(pipe, _DPST_HIST_BIN_A, _DPST_HIST_BIN_B) +#define DPST_HIST_BIN_BUSY REG_BIT(31) +#define DPST_HIST_BIN_DATA_MASK REG_GENMASK(30, 0) + +#define _DPST_IE_BIN_A 0x490CC +#define _DPST_IE_BIN_B 0x491CC +#define DPST_IE_BIN(pipe) _MMIO_PIPE(pipe, _DPST_IE_BIN_A, _DPST_IE_BIN_B) +#define DPST_IE_BIN_DATA_MASK REG_GENMASK(9, 0) +#define DPST_IE_BIN_DATA(val) REG_FIELD_PREP(DPST_IE_BIN_DATA_MASK, val) + +#define _DPST_IE_INDEX_A 0x490DC +#define _DPST_IE_INDEX_B 0x491DC +#define DPST_IE_INDEX(pipe) _MMIO_PIPE(pipe, _DPST_IE_INDEX_A, _DPST_IE_INDEX_B) +#define DPST_IE_BIN_INDEX_MASK REG_GENMASK(6, 0) +#define DPST_IE_BIN_INDEX(val) REG_FIELD_PREP(DPST_IE_BIN_INDEX_MASK, val) + #endif /* __INTEL_HISTOGRAM_REGS_H__ */
In Display 20+, new registers are added for setting index, reading histogram and writing the IET. v2: Removed duplicate code (Jani) v3: Moved histogram core changes to earlier patches (Jani/Suraj) v4: Rebased after addressing comments on patch 1 Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com> --- .../gpu/drm/i915/display/intel_histogram.c | 111 +++++++++++++----- .../drm/i915/display/intel_histogram_regs.h | 25 ++++ 2 files changed, 105 insertions(+), 31 deletions(-)