| Message ID | 20241119-topic-sm8x50-gpu-bw-vote-v2-11-4deb87be2498@linaro.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | drm/msm: adreno: add support for DDR bandwidth scaling via GMU | expand |
On Tue, Nov 19, 2024 at 06:56:46PM +0100, Neil Armstrong wrote: > Each GPU OPP requires a specific peak DDR bandwidth, let's add > those to each OPP and also the related interconnect path. > > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8650.dtsi | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi > index 01ac3769ffa62ffb83c5c51878e2823e1982eb67..331c5140c16bf013190d6da136c0920009d2646b 100644 > --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi > @@ -2636,6 +2636,9 @@ gpu: gpu@3d00000 { > qcom,gmu = <&gmu>; > #cooling-cells = <2>; > > + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; QCOM_ICC_TAG_ALWAYS > + interconnect-names = "gfx-mem"; > + > status = "disabled"; > > zap-shader { > @@ -2649,56 +2652,67 @@ gpu_opp_table: opp-table { > opp-231000000 { > opp-hz = /bits/ 64 <231000000>; > opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; > + opp-peak-kBps = <2136718>; > }; > > opp-310000000 { > opp-hz = /bits/ 64 <310000000>; > opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; > + opp-peak-kBps = <6074218>; > }; > > opp-366000000 { > opp-hz = /bits/ 64 <366000000>; > opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; > + opp-peak-kBps = <6074218>; > }; > > opp-422000000 { > opp-hz = /bits/ 64 <422000000>; > opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; > + opp-peak-kBps = <8171875>; > }; > > opp-500000000 { > opp-hz = /bits/ 64 <500000000>; > opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; > + opp-peak-kBps = <8171875>; > }; > > opp-578000000 { > opp-hz = /bits/ 64 <578000000>; > opp-level = <RPMH_REGULATOR_LEVEL_SVS>; > + opp-peak-kBps = <12449218>; > }; > > opp-629000000 { > opp-hz = /bits/ 64 <629000000>; > opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; > + opp-peak-kBps = <12449218>; > }; > > opp-680000000 { > opp-hz = /bits/ 64 <680000000>; > opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; > + opp-peak-kBps = <16500000>; > }; > > opp-720000000 { > opp-hz = /bits/ 64 <720000000>; > opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; > + opp-peak-kBps = <16500000>; > }; > > opp-770000000 { > opp-hz = /bits/ 64 <770000000>; > opp-level = <RPMH_REGULATOR_LEVEL_NOM>; > + opp-peak-kBps = <16500000>; > }; > > opp-834000000 { > opp-hz = /bits/ 64 <834000000>; > opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; > + opp-peak-kBps = <16500000>; > }; > }; > }; > > -- > 2.34.1 >
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 01ac3769ffa62ffb83c5c51878e2823e1982eb67..331c5140c16bf013190d6da136c0920009d2646b 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2636,6 +2636,9 @@ gpu: gpu@3d00000 { qcom,gmu = <&gmu>; #cooling-cells = <2>; + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "gfx-mem"; + status = "disabled"; zap-shader { @@ -2649,56 +2652,67 @@ gpu_opp_table: opp-table { opp-231000000 { opp-hz = /bits/ 64 <231000000>; opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; + opp-peak-kBps = <2136718>; }; opp-310000000 { opp-hz = /bits/ 64 <310000000>; opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; + opp-peak-kBps = <6074218>; }; opp-366000000 { opp-hz = /bits/ 64 <366000000>; opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; + opp-peak-kBps = <6074218>; }; opp-422000000 { opp-hz = /bits/ 64 <422000000>; opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + opp-peak-kBps = <8171875>; }; opp-500000000 { opp-hz = /bits/ 64 <500000000>; opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; + opp-peak-kBps = <8171875>; }; opp-578000000 { opp-hz = /bits/ 64 <578000000>; opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + opp-peak-kBps = <12449218>; }; opp-629000000 { opp-hz = /bits/ 64 <629000000>; opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; + opp-peak-kBps = <12449218>; }; opp-680000000 { opp-hz = /bits/ 64 <680000000>; opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + opp-peak-kBps = <16500000>; }; opp-720000000 { opp-hz = /bits/ 64 <720000000>; opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; + opp-peak-kBps = <16500000>; }; opp-770000000 { opp-hz = /bits/ 64 <770000000>; opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + opp-peak-kBps = <16500000>; }; opp-834000000 { opp-hz = /bits/ 64 <834000000>; opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + opp-peak-kBps = <16500000>; }; }; };
Each GPU OPP requires a specific peak DDR bandwidth, let's add those to each OPP and also the related interconnect path. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+)