| Message ID | 20241120124512.134278-3-angelogioacchino.delregno@collabora.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/mediatek: Add support for HDMIv2 and DDCv2 IPs | expand |
On Wed, 20 Nov 2024 13:45:07 +0100, AngeloGioacchino Del Regno wrote: > Add a binding for the HDMI TX v2 Encoder found in MediaTek MT8195 > and MT8188 SoCs. > > This fully supports the HDMI Specification 2.0b, hence it provides > support for 3D-HDMI, Polarity inversion, up to 16 bits Deep Color, > color spaces including RGB444, YCBCR420/422/444 (ITU601/ITU709) and > xvYCC, with output resolutions up to 3840x2160p@60Hz. > > Moreover, it also supports HDCP 1.4 and 2.3, Variable Refresh Rate > (VRR) and Consumer Electronics Control (CEC). > > This IP also includes support for HDMI Audio, including IEC60958 > and IEC61937 SPDIF, 8-channel PCM, DSD, and other lossless audio > according to HDMI 2.0. > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > .../mediatek/mediatek,mt8195-hdmi.yaml | 150 ++++++++++++++++++ > 1 file changed, 150 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.example.dtb: hdmi-tx@1c300000: Additional properties are not allowed ('#sound-dai-cells' was unexpected) from schema $id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi.yaml# doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20241120124512.134278-3-angelogioacchino.delregno@collabora.com The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
Hi, Angelo: On Wed, 2024-11-20 at 13:45 +0100, AngeloGioacchino Del Regno wrote: > External email : Please do not click links or open attachments until you have verified the sender or the content. > > > Add a binding for the HDMI TX v2 Encoder found in MediaTek MT8195 > and MT8188 SoCs. > > This fully supports the HDMI Specification 2.0b, hence it provides > support for 3D-HDMI, Polarity inversion, up to 16 bits Deep Color, > color spaces including RGB444, YCBCR420/422/444 (ITU601/ITU709) and > xvYCC, with output resolutions up to 3840x2160p@60Hz. > > Moreover, it also supports HDCP 1.4 and 2.3, Variable Refresh Rate > (VRR) and Consumer Electronics Control (CEC). > > This IP also includes support for HDMI Audio, including IEC60958 > and IEC61937 SPDIF, 8-channel PCM, DSD, and other lossless audio > according to HDMI 2.0. > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > .../mediatek/mediatek,mt8195-hdmi.yaml | 150 ++++++++++++++++++ > 1 file changed, 150 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml > new file mode 100644 > index 000000000000..273a8871461e > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml > @@ -0,0 +1,150 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi.yaml*__;Iw!!CTRNKA9wMg0ARbw!lu0D_C3TwQ2-02jWYABnMIQ8vEoUwP0O4gbQndJnPUMpdi6wXdAHra9ivCfB7zoelDI7qsS20YdRlmP4bEKAABletXFX$ > +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!lu0D_C3TwQ2-02jWYABnMIQ8vEoUwP0O4gbQndJnPUMpdi6wXdAHra9ivCfB7zoelDI7qsS20YdRlmP4bEKAAFlnY-KY$ > + > +title: MediaTek HDMI-TX v2 Encoder > + > +maintainers: > + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > + - CK Hu <ck.hu@mediatek.com> > + > +description: | > + The MediaTek HDMI-TX v2 encoder can generate HDMI format data based on > + the HDMI Specification 2.0b. > + > +properties: > + compatible: > + enum: > + - mediatek,mt8188-hdmi-tx > + - mediatek,mt8195-hdmi-tx > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + items: > + - description: HDMI APB clock > + - description: HDCP top clock > + - description: HDCP reference clock > + - description: VPP HDMI Split clock I would like to know more about HDMI v2. Would you map each v2 clock to v1 clock? If one clock has no mapping, is it a new feature that v1 does not has? Regards, CK > + > + clock-names: > + items: > + - const: bus > + - const: hdcp > + - const: hdcp24m > + - const: hdmi-split > + > > -- > 2.47.0 >
Il 28/11/24 07:02, CK Hu (胡俊光) ha scritto: > Hi, Angelo: > > On Wed, 2024-11-20 at 13:45 +0100, AngeloGioacchino Del Regno wrote: >> External email : Please do not click links or open attachments until you have verified the sender or the content. >> >> >> Add a binding for the HDMI TX v2 Encoder found in MediaTek MT8195 >> and MT8188 SoCs. >> >> This fully supports the HDMI Specification 2.0b, hence it provides >> support for 3D-HDMI, Polarity inversion, up to 16 bits Deep Color, >> color spaces including RGB444, YCBCR420/422/444 (ITU601/ITU709) and >> xvYCC, with output resolutions up to 3840x2160p@60Hz. >> >> Moreover, it also supports HDCP 1.4 and 2.3, Variable Refresh Rate >> (VRR) and Consumer Electronics Control (CEC). >> >> This IP also includes support for HDMI Audio, including IEC60958 >> and IEC61937 SPDIF, 8-channel PCM, DSD, and other lossless audio >> according to HDMI 2.0. >> >> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> >> --- >> .../mediatek/mediatek,mt8195-hdmi.yaml | 150 ++++++++++++++++++ >> 1 file changed, 150 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml >> >> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml >> new file mode 100644 >> index 000000000000..273a8871461e >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml >> @@ -0,0 +1,150 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi.yaml*__;Iw!!CTRNKA9wMg0ARbw!lu0D_C3TwQ2-02jWYABnMIQ8vEoUwP0O4gbQndJnPUMpdi6wXdAHra9ivCfB7zoelDI7qsS20YdRlmP4bEKAABletXFX$ >> +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!lu0D_C3TwQ2-02jWYABnMIQ8vEoUwP0O4gbQndJnPUMpdi6wXdAHra9ivCfB7zoelDI7qsS20YdRlmP4bEKAAFlnY-KY$ >> + >> +title: MediaTek HDMI-TX v2 Encoder >> + >> +maintainers: >> + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> >> + - CK Hu <ck.hu@mediatek.com> >> + >> +description: | >> + The MediaTek HDMI-TX v2 encoder can generate HDMI format data based on >> + the HDMI Specification 2.0b. >> + >> +properties: >> + compatible: >> + enum: >> + - mediatek,mt8188-hdmi-tx >> + - mediatek,mt8195-hdmi-tx >> + >> + reg: >> + maxItems: 1 >> + >> + interrupts: >> + maxItems: 1 >> + >> + clocks: >> + items: >> + - description: HDMI APB clock >> + - description: HDCP top clock >> + - description: HDCP reference clock >> + - description: VPP HDMI Split clock > > I would like to know more about HDMI v2. > Would you map each v2 clock to v1 clock? > If one clock has no mapping, is it a new feature that v1 does not has? > The HDMIv2 HW block seems to be almost completely different from the v1, and it is also interconnected in a different way compared to MT8173 (the path goes through VPP1, while the v1 is just direct to DPI/MMSYS). The v1 block had specific clocks for the audio (i2s, I believe) and for the SPDIF, and I have no idea how v1 does HDCP, but I don't see any specific clock for that. The v2 block is clocked from the HDCP clock, the (apb) bus has its own clock, and the video out needs the vpp split clock. It's just different, and we can't shove the v2 binding inside of the v1 one, but even if we could, since the v2 block is *that much* different from v1, it'd be a mistake to do so. Since the binding describes hardware, and since this v2 HW is *very* different from v1, it needs a new binding document, that is true even if you find a way to get the clocks to match (which is not possible, anyway). Cheers, Angelo > Regards, > CK > >> + >> + clock-names: >> + items: >> + - const: bus >> + - const: hdcp >> + - const: hdcp24m >> + - const: hdmi-split >> + >> >> -- >> 2.47.0 >>
On Thu, 2024-11-28 at 11:32 +0100, AngeloGioacchino Del Regno wrote: > External email : Please do not click links or open attachments until you have verified the sender or the content. > > > Il 28/11/24 07:02, CK Hu (胡俊光) ha scritto: > > Hi, Angelo: > > > > On Wed, 2024-11-20 at 13:45 +0100, AngeloGioacchino Del Regno wrote: > > > External email : Please do not click links or open attachments until you have verified the sender or the content. > > > > > > > > > Add a binding for the HDMI TX v2 Encoder found in MediaTek MT8195 > > > and MT8188 SoCs. > > > > > > This fully supports the HDMI Specification 2.0b, hence it provides > > > support for 3D-HDMI, Polarity inversion, up to 16 bits Deep Color, > > > color spaces including RGB444, YCBCR420/422/444 (ITU601/ITU709) and > > > xvYCC, with output resolutions up to 3840x2160p@60Hz. > > > > > > Moreover, it also supports HDCP 1.4 and 2.3, Variable Refresh Rate > > > (VRR) and Consumer Electronics Control (CEC). > > > > > > This IP also includes support for HDMI Audio, including IEC60958 > > > and IEC61937 SPDIF, 8-channel PCM, DSD, and other lossless audio > > > according to HDMI 2.0. > > > > > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > > > --- > > > .../mediatek/mediatek,mt8195-hdmi.yaml | 150 ++++++++++++++++++ > > > 1 file changed, 150 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml > > > > > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml > > > new file mode 100644 > > > index 000000000000..273a8871461e > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml > > > @@ -0,0 +1,150 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi.yaml*__;Iw!!CTRNKA9wMg0ARbw!lu0D_C3TwQ2-02jWYABnMIQ8vEoUwP0O4gbQndJnPUMpdi6wXdAHra9ivCfB7zoelDI7qsS20YdRlmP4bEKAABletXFX$ > > > +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!lu0D_C3TwQ2-02jWYABnMIQ8vEoUwP0O4gbQndJnPUMpdi6wXdAHra9ivCfB7zoelDI7qsS20YdRlmP4bEKAAFlnY-KY$ > > > + > > > +title: MediaTek HDMI-TX v2 Encoder > > > + > > > +maintainers: > > > + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > > > + - CK Hu <ck.hu@mediatek.com> > > > + > > > +description: | > > > + The MediaTek HDMI-TX v2 encoder can generate HDMI format data based on > > > + the HDMI Specification 2.0b. > > > + > > > +properties: > > > + compatible: > > > + enum: > > > + - mediatek,mt8188-hdmi-tx > > > + - mediatek,mt8195-hdmi-tx > > > + > > > + reg: > > > + maxItems: 1 > > > + > > > + interrupts: > > > + maxItems: 1 > > > + > > > + clocks: > > > + items: > > > + - description: HDMI APB clock > > > + - description: HDCP top clock > > > + - description: HDCP reference clock > > > + - description: VPP HDMI Split clock > > > > I would like to know more about HDMI v2. > > Would you map each v2 clock to v1 clock? > > If one clock has no mapping, is it a new feature that v1 does not has? > > > > The HDMIv2 HW block seems to be almost completely different from the v1, and > it is also interconnected in a different way compared to MT8173 (the path goes > through VPP1, while the v1 is just direct to DPI/MMSYS). > > The v1 block had specific clocks for the audio (i2s, I believe) and for the SPDIF, > and I have no idea how v1 does HDCP, but I don't see any specific clock for that. > > The v2 block is clocked from the HDCP clock, the (apb) bus has its own clock, and > the video out needs the vpp split clock. > > It's just different, and we can't shove the v2 binding inside of the v1 one, but > even if we could, since the v2 block is *that much* different from v1, it'd be a > mistake to do so. > > Since the binding describes hardware, and since this v2 HW is *very* different > from v1, it needs a new binding document, that is true even if you find a way to > get the clocks to match (which is not possible, anyway). v2 indeed is very different from v1, so it's not necessary to merge binding document. I would like to have more information about the difference in binding document, so that we could clearly understand that v1 and v2 are so different. I think pixel clock is important for HDMI hardware, but I do not see it in HDMI v2. It is better has some documentation about why pixel clock disappear in HDMI v2. I've some 'WHY' about v2. Why no audio clock in v2? Audio control part is moved out of HDMI block? For HDCP, maybe v1 driver has not implement it so forget to add it in binding document. So just skip the HDCP. The four clock in v2 does not exist in v1, so what is the function of each one? If possible, ask MediaTek staff for more information. Regards, CK > > Cheers, > Angelo > > > Regards, > > CK > > > > > + > > > + clock-names: > > > + items: > > > + - const: bus > > > + - const: hdcp > > > + - const: hdcp24m > > > + - const: hdmi-split > > > + > > > > > > -- > > > 2.47.0 > > > > >
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml new file mode 100644 index 000000000000..273a8871461e --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml @@ -0,0 +1,150 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek HDMI-TX v2 Encoder + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + - CK Hu <ck.hu@mediatek.com> + +description: | + The MediaTek HDMI-TX v2 encoder can generate HDMI format data based on + the HDMI Specification 2.0b. + +properties: + compatible: + enum: + - mediatek,mt8188-hdmi-tx + - mediatek,mt8195-hdmi-tx + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: HDMI APB clock + - description: HDCP top clock + - description: HDCP reference clock + - description: VPP HDMI Split clock + + clock-names: + items: + - const: bus + - const: hdcp + - const: hdcp24m + - const: hdmi-split + + i2c: + type: object + $ref: /schemas/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml + unevaluatedProperties: false + description: The HDMI DDC IP + + phys: + maxItems: 1 + + phy-names: + items: + - const: hdmi + + pinctrl-0: true + + pinctrl-names: + items: + - const: default + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: + Input port, usually connected to the output port of a DPI + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: + Output port that must be connected either to the input port of + a HDMI connector node containing a ddc-i2c-bus, or to the input + port of an attached bridge chip, such as a SlimPort transmitter. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - power-domains + - phys + - phy-names + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mt8195-clk.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/mt8195-power.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + hdmi-tx@1c300000 { + compatible = "mediatek,mt8195-hdmi-tx"; + reg = <0 0x1c300000 0 0x1000>; + clocks = <&topckgen CLK_TOP_HDMI_APB>, + <&topckgen CLK_TOP_HDCP>, + <&topckgen CLK_TOP_HDCP_24M>, + <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>; + clock-names = "bus", "hdcp", "hdcp24m", "hdmi-split"; + interrupts = <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH 0>; + phys = <&hdmi_phy>; + phy-names = "hdmi"; + power-domains = <&spm MT8195_POWER_DOMAIN_HDMI_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins>; + #sound-dai-cells = <0>; + + hdmitx_ddc: i2c { + compatible = "mediatek,mt8195-hdmi-ddc"; + clocks = <&clk26m>; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_in: endpoint { + remote-endpoint = <&dpi1_out>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + };
Add a binding for the HDMI TX v2 Encoder found in MediaTek MT8195 and MT8188 SoCs. This fully supports the HDMI Specification 2.0b, hence it provides support for 3D-HDMI, Polarity inversion, up to 16 bits Deep Color, color spaces including RGB444, YCBCR420/422/444 (ITU601/ITU709) and xvYCC, with output resolutions up to 3840x2160p@60Hz. Moreover, it also supports HDCP 1.4 and 2.3, Variable Refresh Rate (VRR) and Consumer Electronics Control (CEC). This IP also includes support for HDMI Audio, including IEC60958 and IEC61937 SPDIF, 8-channel PCM, DSD, and other lossless audio according to HDMI 2.0. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- .../mediatek/mediatek,mt8195-hdmi.yaml | 150 ++++++++++++++++++ 1 file changed, 150 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml