diff mbox series

[v2] scsi: qla1280: Fix hw revision numbering for ISP1020/1040

Message ID 20241113225636.2276-1-linmag7@gmail.com (mailing list archive)
State Under Review
Headers show
Series [v2] scsi: qla1280: Fix hw revision numbering for ISP1020/1040 | expand

Commit Message

Magnus Lindholm Nov. 13, 2024, 10:51 p.m. UTC
Fix the hardware revision numbering for Qlogic ISP1020/1040 boards.
HWMASK suggest that the revision number only needs four bits, this is
consistent with how NetBSD does things in their ISP driver. verified on
a IPS1040B which is seen as rev 5 not as BIT_4.

Signed-off-by: Magnus Lindholm <linmag7@gmail.com>
---
 drivers/scsi/qla1280.h | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

Comments

Christoph Hellwig Nov. 14, 2024, 4:16 a.m. UTC | #1
Looks good:

Reviewed-by: Christoph Hellwig <hch@lst.de>
Martin K. Petersen Nov. 21, 2024, 2:33 a.m. UTC | #2
Magnus,

> Fix the hardware revision numbering for Qlogic ISP1020/1040 boards.
> HWMASK suggest that the revision number only needs four bits, this is
> consistent with how NetBSD does things in their ISP driver. verified
> on a IPS1040B which is seen as rev 5 not as BIT_4.

Applied to 6.13/scsi-staging, thanks!
diff mbox series

Patch

diff --git a/drivers/scsi/qla1280.h b/drivers/scsi/qla1280.h
index d309e2ca14de..796cb493a4df 100644
--- a/drivers/scsi/qla1280.h
+++ b/drivers/scsi/qla1280.h
@@ -116,12 +116,12 @@  struct device_reg {
 	uint16_t id_h;		/* ID high */
 	uint16_t cfg_0;		/* Configuration 0 */
 #define ISP_CFG0_HWMSK   0x000f	/* Hardware revision mask */
-#define ISP_CFG0_1020    BIT_0	/* ISP1020 */
-#define ISP_CFG0_1020A	 BIT_1	/* ISP1020A */
-#define ISP_CFG0_1040	 BIT_2	/* ISP1040 */
-#define ISP_CFG0_1040A	 BIT_3	/* ISP1040A */
-#define ISP_CFG0_1040B	 BIT_4	/* ISP1040B */
-#define ISP_CFG0_1040C	 BIT_5	/* ISP1040C */
+#define ISP_CFG0_1020    1	/* ISP1020 */
+#define ISP_CFG0_1020A	 2	/* ISP1020A */
+#define ISP_CFG0_1040	 3	/* ISP1040 */
+#define ISP_CFG0_1040A	 4	/* ISP1040A */
+#define ISP_CFG0_1040B	 5	/* ISP1040B */
+#define ISP_CFG0_1040C	 6	/* ISP1040C */
 	uint16_t cfg_1;		/* Configuration 1 */
 #define ISP_CFG1_F128    BIT_6  /* 128-byte FIFO threshold */
 #define ISP_CFG1_F64     BIT_4|BIT_5 /* 128-byte FIFO threshold */