| Message ID | 20240412031208.30688-1-shuijing.li@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] mediatek: dsi: Correct calculation formula of PHY Timing | expand |
Hi, Shuijing: On Fri, 2024-04-12 at 11:11 +0800, Shuijing Li wrote: > This patch correct calculation formula of PHY timing. > The spec define HS-PREPARE should be from 40ns+4*UI(44ns) to > 85ns+6*UI(91ns). But current duration is 88ns and is near the > boundary. > So this patch make the duration to 64ns so it is near the safe range. Reviewed-by: CK Hu <ck.hu@mediatek.com> > > Signed-off-by: Shuijing Li <shuijing.li@mediatek.com> > --- > Changes in v2: > Add a commit to describe the improvements to this patch in detail, > per suggestion frome previous thread: > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20240315072945.19502-1-shuijing.li@mediatek.com/__;!!CTRNKA9wMg0ARbw!izTVzhN1oe9FMDawQlr9R7PNf0n6z7ZgcSw8IUcNfcZxAJQ6Rja9aHaUoL7lISbdMHUvONao6-3_wZbs0aH72A$ > > --- > drivers/gpu/drm/mediatek/mtk_dsi.c | 33 +++++++++++++++------------- > -- > 1 file changed, 17 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c > b/drivers/gpu/drm/mediatek/mtk_dsi.c > index a2fdfc8ddb15..d1bd7d671880 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c > @@ -235,22 +235,23 @@ static void mtk_dsi_phy_timconfig(struct > mtk_dsi *dsi) > u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, 1000000); > struct mtk_phy_timing *timing = &dsi->phy_timing; > > - timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1; > - timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000; > - timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + > 1 - > - timing->da_hs_prepare; > - timing->da_hs_trail = timing->da_hs_prepare + 1; > - > - timing->ta_go = 4 * timing->lpx - 2; > - timing->ta_sure = timing->lpx + 2; > - timing->ta_get = 4 * timing->lpx; > - timing->da_hs_exit = 2 * timing->lpx + 1; > - > - timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000); > - timing->clk_hs_post = timing->clk_hs_prepare + 8; > - timing->clk_hs_trail = timing->clk_hs_prepare; > - timing->clk_hs_zero = timing->clk_hs_trail * 4; > - timing->clk_hs_exit = 2 * timing->clk_hs_trail; > + timing->lpx = (80 * data_rate_mhz / (8 * 1000)) + 1; > + timing->da_hs_prepare = (59 * data_rate_mhz + 4 * 1000) / 8000 > + 1; > + timing->da_hs_zero = (163 * data_rate_mhz + 11 * 1000) / 8000 + > 1 - > + timing->da_hs_prepare; > + timing->da_hs_trail = (78 * data_rate_mhz + 7 * 1000) / 8000 + > 1; > + > + timing->ta_go = 4 * timing->lpx; > + timing->ta_sure = 3 * timing->lpx / 2; > + timing->ta_get = 5 * timing->lpx; > + timing->da_hs_exit = (118 * data_rate_mhz / (8 * 1000)) + 1; > + > + timing->clk_hs_prepare = (57 * data_rate_mhz / (8 * 1000)) + 1; > + timing->clk_hs_post = (65 * data_rate_mhz + 53 * 1000) / 8000 + > 1; > + timing->clk_hs_trail = (78 * data_rate_mhz + 7 * 1000) / 8000 + > 1; > + timing->clk_hs_zero = (330 * data_rate_mhz / (8 * 1000)) + 1 - > + timing->clk_hs_prepare; > + timing->clk_hs_exit = (118 * data_rate_mhz / (8 * 1000)) + 1; > > timcon0 = timing->lpx | timing->da_hs_prepare << 8 | > timing->da_hs_zero << 16 | timing->da_hs_trail << 24;
Am Fri, 12 Apr 2024 11:11:39 +0800 schrieb Shuijing Li <shuijing.li@mediatek.com>: > This patch correct calculation formula of PHY timing. > The spec define HS-PREPARE should be from 40ns+4*UI(44ns) to > 85ns+6*UI(91ns). But current duration is 88ns and is near the > boundary. So this patch make the duration to 64ns so it is near the > safe range. Hi Shuijing, with this patch the panel in the Tentacruel ASUS Chromebook CM14 (CM1402F) flickers. There are 1 or 2 times per second a black panel. Stable Kernel 6.11.5 and mainline 6.12-rc4 works only when I reverse this patch. There's a bug inside. Can you please check that? Best regards Jens > > Signed-off-by: Shuijing Li <shuijing.li@mediatek.com> > --- > Changes in v2: > Add a commit to describe the improvements to this patch in detail, > per suggestion frome previous thread: > https://patchwork.kernel.org/project/linux-mediatek/patch/20240315072945.19502-1-shuijing.li@mediatek.com/ > --- > drivers/gpu/drm/mediatek/mtk_dsi.c | 33 > +++++++++++++++--------------- 1 file changed, 17 insertions(+), 16 > deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c > b/drivers/gpu/drm/mediatek/mtk_dsi.c index a2fdfc8ddb15..d1bd7d671880 > 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c > @@ -235,22 +235,23 @@ static void mtk_dsi_phy_timconfig(struct > mtk_dsi *dsi) u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, > 1000000); struct mtk_phy_timing *timing = &dsi->phy_timing; > > - timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1; > - timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / > 8000; > - timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / > 8000 + 1 - > - timing->da_hs_prepare; > - timing->da_hs_trail = timing->da_hs_prepare + 1; > - > - timing->ta_go = 4 * timing->lpx - 2; > - timing->ta_sure = timing->lpx + 2; > - timing->ta_get = 4 * timing->lpx; > - timing->da_hs_exit = 2 * timing->lpx + 1; > - > - timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000); > - timing->clk_hs_post = timing->clk_hs_prepare + 8; > - timing->clk_hs_trail = timing->clk_hs_prepare; > - timing->clk_hs_zero = timing->clk_hs_trail * 4; > - timing->clk_hs_exit = 2 * timing->clk_hs_trail; > + timing->lpx = (80 * data_rate_mhz / (8 * 1000)) + 1; > + timing->da_hs_prepare = (59 * data_rate_mhz + 4 * 1000) / > 8000 + 1; > + timing->da_hs_zero = (163 * data_rate_mhz + 11 * 1000) / > 8000 + 1 - > + timing->da_hs_prepare; > + timing->da_hs_trail = (78 * data_rate_mhz + 7 * 1000) / 8000 > + 1; + > + timing->ta_go = 4 * timing->lpx; > + timing->ta_sure = 3 * timing->lpx / 2; > + timing->ta_get = 5 * timing->lpx; > + timing->da_hs_exit = (118 * data_rate_mhz / (8 * 1000)) + 1; > + > + timing->clk_hs_prepare = (57 * data_rate_mhz / (8 * 1000)) + > 1; > + timing->clk_hs_post = (65 * data_rate_mhz + 53 * 1000) / > 8000 + 1; > + timing->clk_hs_trail = (78 * data_rate_mhz + 7 * 1000) / > 8000 + 1; > + timing->clk_hs_zero = (330 * data_rate_mhz / (8 * 1000)) + 1 > - > + timing->clk_hs_prepare; > + timing->clk_hs_exit = (118 * data_rate_mhz / (8 * 1000)) + 1; > > timcon0 = timing->lpx | timing->da_hs_prepare << 8 | > timing->da_hs_zero << 16 | timing->da_hs_trail << > 24;
Hi, Shuijing: On Sun, 2024-10-27 at 14:32 +0100, Jens Ziller wrote: > External email : Please do not click links or open attachments until you have verified the sender or the content. > > > Am Fri, 12 Apr 2024 11:11:39 +0800 > schrieb Shuijing Li <shuijing.li@mediatek.com>: > > > This patch correct calculation formula of PHY timing. > > The spec define HS-PREPARE should be from 40ns+4*UI(44ns) to > > 85ns+6*UI(91ns). But current duration is 88ns and is near the > > boundary. So this patch make the duration to 64ns so it is near the > > safe range. > > Hi Shuijing, > > with this patch the panel in the Tentacruel ASUS Chromebook CM14 > (CM1402F) flickers. There are 1 or 2 times per second a black panel. > Stable Kernel 6.11.5 and mainline 6.12-rc4 works only when I reverse > this patch. There's a bug inside. Can you please check that? Please help Jens to fix this bug. Otherwise, I've to revert this patch. Regards, CK > > Best regards > Jens > > > > > Signed-off-by: Shuijing Li <shuijing.li@mediatek.com> > > --- > > Changes in v2: > > Add a commit to describe the improvements to this patch in detail, > > per suggestion frome previous thread: > > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20240315072945.19502-1-shuijing.li@mediatek.com/__;!!CTRNKA9wMg0ARbw!nA3Auuq2W3qyf3a8OtzDvLICN_xfq5zUozp_-Wo7Q4jR9l6qKlxiWNC4TZPXQa8W08veWhokHyRrvCodcpg$ > > --- > > drivers/gpu/drm/mediatek/mtk_dsi.c | 33 > > +++++++++++++++--------------- 1 file changed, 17 insertions(+), 16 > > deletions(-) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c > > b/drivers/gpu/drm/mediatek/mtk_dsi.c index a2fdfc8ddb15..d1bd7d671880 > > 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c > > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c > > @@ -235,22 +235,23 @@ static void mtk_dsi_phy_timconfig(struct > > mtk_dsi *dsi) u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, > > 1000000); struct mtk_phy_timing *timing = &dsi->phy_timing; > > > > - timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1; > > - timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / > > 8000; > > - timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / > > 8000 + 1 - > > - timing->da_hs_prepare; > > - timing->da_hs_trail = timing->da_hs_prepare + 1; > > - > > - timing->ta_go = 4 * timing->lpx - 2; > > - timing->ta_sure = timing->lpx + 2; > > - timing->ta_get = 4 * timing->lpx; > > - timing->da_hs_exit = 2 * timing->lpx + 1; > > - > > - timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000); > > - timing->clk_hs_post = timing->clk_hs_prepare + 8; > > - timing->clk_hs_trail = timing->clk_hs_prepare; > > - timing->clk_hs_zero = timing->clk_hs_trail * 4; > > - timing->clk_hs_exit = 2 * timing->clk_hs_trail; > > + timing->lpx = (80 * data_rate_mhz / (8 * 1000)) + 1; > > + timing->da_hs_prepare = (59 * data_rate_mhz + 4 * 1000) / > > 8000 + 1; > > + timing->da_hs_zero = (163 * data_rate_mhz + 11 * 1000) / > > 8000 + 1 - > > + timing->da_hs_prepare; > > + timing->da_hs_trail = (78 * data_rate_mhz + 7 * 1000) / 8000 > > + 1; + > > + timing->ta_go = 4 * timing->lpx; > > + timing->ta_sure = 3 * timing->lpx / 2; > > + timing->ta_get = 5 * timing->lpx; > > + timing->da_hs_exit = (118 * data_rate_mhz / (8 * 1000)) + 1; > > + > > + timing->clk_hs_prepare = (57 * data_rate_mhz / (8 * 1000)) + > > 1; > > + timing->clk_hs_post = (65 * data_rate_mhz + 53 * 1000) / > > 8000 + 1; > > + timing->clk_hs_trail = (78 * data_rate_mhz + 7 * 1000) / > > 8000 + 1; > > + timing->clk_hs_zero = (330 * data_rate_mhz / (8 * 1000)) + 1 > > - > > + timing->clk_hs_prepare; > > + timing->clk_hs_exit = (118 * data_rate_mhz / (8 * 1000)) + 1; > > > > timcon0 = timing->lpx | timing->da_hs_prepare << 8 | > > timing->da_hs_zero << 16 | timing->da_hs_trail << > > 24; > >
Am Thu, 21 Nov 2024 03:50:02 +0000 schrieb CK Hu (胡俊光) <ck.hu@mediatek.com>: > Hi, Shuijing: > > On Sun, 2024-10-27 at 14:32 +0100, Jens Ziller wrote: > > External email : Please do not click links or open attachments > > until you have verified the sender or the content. > > > > > > Am Fri, 12 Apr 2024 11:11:39 +0800 > > schrieb Shuijing Li <shuijing.li@mediatek.com>: > > > > > This patch correct calculation formula of PHY timing. > > > The spec define HS-PREPARE should be from 40ns+4*UI(44ns) to > > > 85ns+6*UI(91ns). But current duration is 88ns and is near the > > > boundary. So this patch make the duration to 64ns so it is near > > > the safe range. > > > > Hi Shuijing, > > > > with this patch the panel in the Tentacruel ASUS Chromebook CM14 > > (CM1402F) flickers. There are 1 or 2 times per second a black panel. > > Stable Kernel 6.11.5 and mainline 6.12-rc4 works only when I reverse > > this patch. There's a bug inside. Can you please check that? > > Please help Jens to fix this bug. > Otherwise, I've to revert this patch. > > Regards, > CK I'am not be able to fix that. This patch must be reverted that the actual kernel runs on my Chromebook. Please revert this patch. Regards Jens > > > > > Best regards > > Jens > > > > > > > > Signed-off-by: Shuijing Li <shuijing.li@mediatek.com> > > > --- > > > Changes in v2: > > > Add a commit to describe the improvements to this patch in detail, > > > per suggestion frome previous thread: > > > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20240315072945.19502-1-shuijing.li@mediatek.com/__;!!CTRNKA9wMg0ARbw!nA3Auuq2W3qyf3a8OtzDvLICN_xfq5zUozp_-Wo7Q4jR9l6qKlxiWNC4TZPXQa8W08veWhokHyRrvCodcpg$ > > > --- > > > drivers/gpu/drm/mediatek/mtk_dsi.c | 33 > > > +++++++++++++++--------------- 1 file changed, 17 insertions(+), > > > 16 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c > > > b/drivers/gpu/drm/mediatek/mtk_dsi.c index > > > a2fdfc8ddb15..d1bd7d671880 100644 --- > > > a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ > > > b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -235,22 +235,23 @@ static > > > void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi) u32 data_rate_mhz > > > = DIV_ROUND_UP(dsi->data_rate, 1000000); struct mtk_phy_timing > > > *timing = &dsi->phy_timing; > > > > > > - timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1; > > > - timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / > > > 8000; > > > - timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / > > > 8000 + 1 - > > > - timing->da_hs_prepare; > > > - timing->da_hs_trail = timing->da_hs_prepare + 1; > > > - > > > - timing->ta_go = 4 * timing->lpx - 2; > > > - timing->ta_sure = timing->lpx + 2; > > > - timing->ta_get = 4 * timing->lpx; > > > - timing->da_hs_exit = 2 * timing->lpx + 1; > > > - > > > - timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000); > > > - timing->clk_hs_post = timing->clk_hs_prepare + 8; > > > - timing->clk_hs_trail = timing->clk_hs_prepare; > > > - timing->clk_hs_zero = timing->clk_hs_trail * 4; > > > - timing->clk_hs_exit = 2 * timing->clk_hs_trail; > > > + timing->lpx = (80 * data_rate_mhz / (8 * 1000)) + 1; > > > + timing->da_hs_prepare = (59 * data_rate_mhz + 4 * 1000) / > > > 8000 + 1; > > > + timing->da_hs_zero = (163 * data_rate_mhz + 11 * 1000) / > > > 8000 + 1 - > > > + timing->da_hs_prepare; > > > + timing->da_hs_trail = (78 * data_rate_mhz + 7 * 1000) / 8000 > > > + 1; + > > > + timing->ta_go = 4 * timing->lpx; > > > + timing->ta_sure = 3 * timing->lpx / 2; > > > + timing->ta_get = 5 * timing->lpx; > > > + timing->da_hs_exit = (118 * data_rate_mhz / (8 * 1000)) + 1; > > > + > > > + timing->clk_hs_prepare = (57 * data_rate_mhz / (8 * 1000)) + > > > 1; > > > + timing->clk_hs_post = (65 * data_rate_mhz + 53 * 1000) / > > > 8000 + 1; > > > + timing->clk_hs_trail = (78 * data_rate_mhz + 7 * 1000) / > > > 8000 + 1; > > > + timing->clk_hs_zero = (330 * data_rate_mhz / (8 * 1000)) + 1 > > > - > > > + timing->clk_hs_prepare; > > > + timing->clk_hs_exit = (118 * data_rate_mhz / (8 * 1000)) + > > > 1; > > > > > > timcon0 = timing->lpx | timing->da_hs_prepare << 8 | > > > timing->da_hs_zero << 16 | timing->da_hs_trail << > > > 24; > > > >
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index a2fdfc8ddb15..d1bd7d671880 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -235,22 +235,23 @@ static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi) u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, 1000000); struct mtk_phy_timing *timing = &dsi->phy_timing; - timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1; - timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000; - timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 - - timing->da_hs_prepare; - timing->da_hs_trail = timing->da_hs_prepare + 1; - - timing->ta_go = 4 * timing->lpx - 2; - timing->ta_sure = timing->lpx + 2; - timing->ta_get = 4 * timing->lpx; - timing->da_hs_exit = 2 * timing->lpx + 1; - - timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000); - timing->clk_hs_post = timing->clk_hs_prepare + 8; - timing->clk_hs_trail = timing->clk_hs_prepare; - timing->clk_hs_zero = timing->clk_hs_trail * 4; - timing->clk_hs_exit = 2 * timing->clk_hs_trail; + timing->lpx = (80 * data_rate_mhz / (8 * 1000)) + 1; + timing->da_hs_prepare = (59 * data_rate_mhz + 4 * 1000) / 8000 + 1; + timing->da_hs_zero = (163 * data_rate_mhz + 11 * 1000) / 8000 + 1 - + timing->da_hs_prepare; + timing->da_hs_trail = (78 * data_rate_mhz + 7 * 1000) / 8000 + 1; + + timing->ta_go = 4 * timing->lpx; + timing->ta_sure = 3 * timing->lpx / 2; + timing->ta_get = 5 * timing->lpx; + timing->da_hs_exit = (118 * data_rate_mhz / (8 * 1000)) + 1; + + timing->clk_hs_prepare = (57 * data_rate_mhz / (8 * 1000)) + 1; + timing->clk_hs_post = (65 * data_rate_mhz + 53 * 1000) / 8000 + 1; + timing->clk_hs_trail = (78 * data_rate_mhz + 7 * 1000) / 8000 + 1; + timing->clk_hs_zero = (330 * data_rate_mhz / (8 * 1000)) + 1 - + timing->clk_hs_prepare; + timing->clk_hs_exit = (118 * data_rate_mhz / (8 * 1000)) + 1; timcon0 = timing->lpx | timing->da_hs_prepare << 8 | timing->da_hs_zero << 16 | timing->da_hs_trail << 24;
This patch correct calculation formula of PHY timing. The spec define HS-PREPARE should be from 40ns+4*UI(44ns) to 85ns+6*UI(91ns). But current duration is 88ns and is near the boundary. So this patch make the duration to 64ns so it is near the safe range. Signed-off-by: Shuijing Li <shuijing.li@mediatek.com> --- Changes in v2: Add a commit to describe the improvements to this patch in detail, per suggestion frome previous thread: https://patchwork.kernel.org/project/linux-mediatek/patch/20240315072945.19502-1-shuijing.li@mediatek.com/ --- drivers/gpu/drm/mediatek/mtk_dsi.c | 33 +++++++++++++++--------------- 1 file changed, 17 insertions(+), 16 deletions(-)