| Message ID | 20241113-add-display-support-for-qcs615-platform-v2-8-2873eb6fb869@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add display support for QCS615 platform | expand |
On Wed, 13 Nov 2024 at 13:53, Fange Zhang <quic_fangez@quicinc.com> wrote: > > From: Li Liu <quic_lliu6@quicinc.com> > > Add display MDSS and DSI configuration for QCS615. > QCS615 has a DP port, and DP support will be added in a later patch. > > Signed-off-by: Li Liu <quic_lliu6@quicinc.com> > Signed-off-by: Fange Zhang <quic_fangez@quicinc.com> > --- > arch/arm64/boot/dts/qcom/qcs615-ride.dts | 109 +++++++++++++++++++++++++++++++ > 1 file changed, 109 insertions(+) This patch has even more feedback that was ignored at v1. Please go to the v1 discussion, respond to _all_ the items, so that we can actually see what got ignored and why. Usually I don't require this (we can all make a mistake and miss an item or two), but with this patchset the number of the comments that were ignored is extremely high.
On 2024/11/13 20:27, Dmitry Baryshkov wrote: > On Wed, 13 Nov 2024 at 13:53, Fange Zhang <quic_fangez@quicinc.com> wrote: >> >> From: Li Liu <quic_lliu6@quicinc.com> >> >> Add display MDSS and DSI configuration for QCS615. >> QCS615 has a DP port, and DP support will be added in a later patch. >> >> Signed-off-by: Li Liu <quic_lliu6@quicinc.com> >> Signed-off-by: Fange Zhang <quic_fangez@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/qcs615-ride.dts | 109 +++++++++++++++++++++++++++++++ >> 1 file changed, 109 insertions(+) > > > This patch has even more feedback that was ignored at v1. Please go to > the v1 discussion, respond to _all_ the items, so that we can actually > see what got ignored and why. Usually I don't require this (we can all > make a mistake and miss an item or two), but with this patchset the > number of the comments that were ignored is extremely high. i am so sorry for the mistake and miss, will update and double confirm all v1 comments. we are preparing v3 to fix them >
diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index ee6cab3924a6d71f29934a8debba3a832882abdd..8b9029e96b07cbef950b074a7412180d6c27d39a 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -202,6 +202,115 @@ &gcc { <&sleep_clk>; }; +&i2c2 { + clock-frequency = <400000>; + pinctrl-0 = <&qup_i2c2_data_clk &ioexp_intr_active &ioexp_reset_active>; + pinctrl-names = "default"; + status = "okay"; + + ioexp: gpio@3e { + compatible = "semtech,sx1509q"; + reg = <0x3e>; + interrupt-parent = <&tlmm>; + interrupts = <58 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + semtech,probe-reset; + pinctrl-names = "default"; + pinctrl-0 = <&dsi_dp_hpd_cfg_pins &dsi_dp_cdet_cfg_pins>; + + // HPD configuration for DSI to DP port + dsi_dp_hpd_cfg_pins: gpio0-cfg { + pins = "gpio0"; + bias-pull-up; + }; + + // Connection detect configuration for DSI to DP port + dsi_dp_cdet_cfg_pins: gpio1-cfg { + pins = "gpio1"; + bias-pull-down; + }; + }; + + i2c-mux@77 { + compatible = "nxp,pca9542"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + anx7625@58 { + compatible = "analogix,anx7625"; + reg = <0x58>; + interrupt-parent = <&ioexp>; + interrupts = <0 0>; + enable-gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>; + wakeup-source; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + anx_7625_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + anx_7625_out: endpoint { + }; + }; + }; + }; + }; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l11a>; + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <&anx_7625_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l5a>; + status = "okay"; +}; + +&tlmm { + ioexp_intr_active: ioexp_intr_active { + pins = "gpio58"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + ioexp_reset_active: ioexp_reset_active { + pins = "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-high; + }; +}; + &qupv3_id_0 { status = "okay"; };