| Message ID | 20241122-switch_gdsc_mode-v1-2-365f097ecbb0@quicinc.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | Use APIs in gdsc genpd to switch gdsc mode for venus v4 core | expand |
On 22/11/2024 10:31, Renjiang Han wrote: > - if (IS_V6(core)) > + if (IS_V6(core) || IS_V4(core)) sdm845 IS_V4() The GDSCs for the clock OTOH are static struct gdsc vcodec0_gdsc = { .gdscr = 0x874, .pd = { .name = "vcodec0_gdsc", }, .cxcs = (unsigned int []){ 0x890, 0x930 }, .cxc_count = 2, .flags = HW_CTRL | POLL_CFG_GDSCR, .pwrsts = PWRSTS_OFF_ON, }; static struct gdsc vcodec1_gdsc = { .gdscr = 0x8b4, .pd = { .name = "vcodec1_gdsc", }, .cxcs = (unsigned int []){ 0x8d0, 0x950 }, .cxc_count = 2, .flags = HW_CTRL | POLL_CFG_GDSCR, .pwrsts = PWRSTS_OFF_ON, }; I can't see how this series will work on 845. --- bod
On Friday, November 22, 2024 8:51 PM, Bryan O'Donoghue wrote: > On 22/11/2024 10:31, Renjiang Han wrote: > > - if (IS_V6(core)) > > + if (IS_V6(core) || IS_V4(core)) > sdm845 IS_V4() > The GDSCs for the clock OTOH are > static struct gdsc vcodec0_gdsc = { > .gdscr = 0x874, > .pd = { > .name = "vcodec0_gdsc", > }, > .cxcs = (unsigned int []){ 0x890, 0x930 }, > .cxc_count = 2, > .flags = HW_CTRL | POLL_CFG_GDSCR, > .pwrsts = PWRSTS_OFF_ON, > }; > static struct gdsc vcodec1_gdsc = { > .gdscr = 0x8b4, > .pd = { > .name = "vcodec1_gdsc", > }, > .cxcs = (unsigned int []){ 0x8d0, 0x950 }, > .cxc_count = 2, > .flags = HW_CTRL | POLL_CFG_GDSCR, > .pwrsts = PWRSTS_OFF_ON, > }; > I can't see how this series will work on 845. Thanks for your review. In [PATCH 1/2] clk: qcom: videocc: Use HW_CTRL_TRIGGER flag for video GDSC's, the gdsc flag will be changed to HW_CTRL_TRIGGER, so the v4 core also needs to use the method of switching GDSC mode like v6. > --- > bod Best Regards, Renjiang
diff --git a/drivers/media/platform/qcom/venus/pm_helpers.c b/drivers/media/platform/qcom/venus/pm_helpers.c index 33a5a659c0ada0ca97eebb5522c5f349f95c49c7..a2062b366d4aedba3eb5e4be456a005847eaec0b 100644 --- a/drivers/media/platform/qcom/venus/pm_helpers.c +++ b/drivers/media/platform/qcom/venus/pm_helpers.c @@ -412,7 +412,7 @@ static int vcodec_control_v4(struct venus_core *core, u32 coreid, bool enable) u32 val; int ret; - if (IS_V6(core)) + if (IS_V6(core) || IS_V4(core)) return dev_pm_genpd_set_hwmode(core->pmdomains->pd_devs[coreid], !enable); else if (coreid == VIDC_CORE_ID_1) { ctrl = core->wrapper_base + WRAPPER_VCODEC0_MMCC_POWER_CONTROL; @@ -450,7 +450,7 @@ static int poweroff_coreid(struct venus_core *core, unsigned int coreid_mask) vcodec_clks_disable(core, core->vcodec0_clks); - if (!IS_V6(core)) { + if (!IS_V6(core) && !IS_V4(core)) { ret = vcodec_control_v4(core, VIDC_CORE_ID_1, false); if (ret) return ret; @@ -468,7 +468,7 @@ static int poweroff_coreid(struct venus_core *core, unsigned int coreid_mask) vcodec_clks_disable(core, core->vcodec1_clks); - if (!IS_V6(core)) { + if (!IS_V6(core) && !IS_V4(core)) { ret = vcodec_control_v4(core, VIDC_CORE_ID_2, false); if (ret) return ret; @@ -491,7 +491,7 @@ static int poweron_coreid(struct venus_core *core, unsigned int coreid_mask) if (ret < 0) return ret; - if (!IS_V6(core)) { + if (!IS_V6(core) && !IS_V4(core)) { ret = vcodec_control_v4(core, VIDC_CORE_ID_1, true); if (ret) return ret; @@ -511,7 +511,7 @@ static int poweron_coreid(struct venus_core *core, unsigned int coreid_mask) if (ret < 0) return ret; - if (!IS_V6(core)) { + if (!IS_V6(core) && !IS_V4(core)) { ret = vcodec_control_v4(core, VIDC_CORE_ID_2, true); if (ret) return ret;
The POWER_CONTROL register addresses are not constant and can vary across the variants. Also as per the HW recommendation, the GDSC mode switching needs to be controlled from respective GDSC register and this is a uniform approach across all the targets. Hence use dev_pm_genpd_set_hwmode() API which controls GDSC mode switching using its respective GDSC register. In venus v4 variants, the vcodec gdsc gets enabled in SW mode by default with new HW_CTRL_TRIGGER flag and there is no need to switch it to SW mode again after enable, hence add check to avoid switching gdsc to SW mode again after gdsc enable. Similarly add check to avoid switching GDSC to HW mode before disabling the GDSC, so GDSC gets enabled in SW mode in the next enable. Signed-off-by: Renjiang Han <quic_renjiang@quicinc.com> --- drivers/media/platform/qcom/venus/pm_helpers.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)