diff mbox series

[04/13] target/mips: Rename gen_move_high32() -> gen_move_high32_tl()

Message ID 20241126131546.66145-5-philmd@linaro.org (mailing list archive)
State New
Headers show
Series target/mips: Simplify some target_ulong registers to 32-bit | expand

Commit Message

Philippe Mathieu-Daudé Nov. 26, 2024, 1:15 p.m. UTC 
MIPS gen_move_high32() takes a target-specific TCGv argument.
Rename it as gen_move_high32_tl() to clarify, like other TCG
core helpers.

Mechanical change doing:

  $ sed -i -e 's/gen_move_high32/gen_move_high32_tl/' \
     $(git grep -l gen_move_high32)

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/mips/tcg/translate.h              |  2 +-
 target/mips/tcg/mxu_translate.c          |  2 +-
 target/mips/tcg/translate.c              | 14 +++++++-------
 target/mips/tcg/nanomips_translate.c.inc |  8 ++++----
 4 files changed, 13 insertions(+), 13 deletions(-)

Comments

Richard Henderson Nov. 26, 2024, 1:51 p.m. UTC | #1 
On 11/26/24 07:15, Philippe Mathieu-Daudé wrote:
> MIPS gen_move_high32() takes a target-specific TCGv argument.
> Rename it as gen_move_high32_tl() to clarify, like other TCG
> core helpers.
> 
> Mechanical change doing:
> 
>    $ sed -i -e 's/gen_move_high32/gen_move_high32_tl/' \
>       $(git grep -l gen_move_high32)
> 
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~
diff mbox series

Patch

diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index 6437180d891..90b8ac0e5b1 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -154,7 +154,7 @@  void check_cop1x(DisasContext *ctx);
 
 void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset);
 void gen_move_low32_tl(TCGv ret, TCGv_i64 arg);
-void gen_move_high32(TCGv ret, TCGv_i64 arg);
+void gen_move_high32_tl(TCGv ret, TCGv_i64 arg);
 void gen_load_gpr_tl(TCGv t, int reg);
 void gen_store_gpr_tl(TCGv t, int reg);
 #if defined(TARGET_MIPS64)
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
index 94aa137cb25..20b8314b478 100644
--- a/target/mips/tcg/mxu_translate.c
+++ b/target/mips/tcg/mxu_translate.c
@@ -4386,7 +4386,7 @@  static void gen_mxu_s32madd_sub(DisasContext *ctx, bool sub, bool uns)
             tcg_gen_add_i64(t3, t3, t2);
         }
         gen_move_low32_tl(t1, t3);
-        gen_move_high32(t0, t3);
+        gen_move_high32_tl(t0, t3);
 
         tcg_gen_mov_tl(cpu_HI[0], t0);
         tcg_gen_mov_tl(cpu_LO[0], t1);
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 5e776136f09..31907c75a62 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -1462,7 +1462,7 @@  void gen_move_low32_tl(TCGv ret, TCGv_i64 arg)
 }
 
 /* Sign-extract the high 32-bits to a target_long.  */
-void gen_move_high32(TCGv ret, TCGv_i64 arg)
+void gen_move_high32_tl(TCGv ret, TCGv_i64 arg)
 {
 #if defined(TARGET_MIPS64)
     tcg_gen_sari_i64(ret, arg, 32);
@@ -3342,7 +3342,7 @@  static void gen_muldiv(DisasContext *ctx, uint32_t opc,
             tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
             tcg_gen_add_i64(t2, t2, t3);
             gen_move_low32_tl(cpu_LO[acc], t2);
-            gen_move_high32(cpu_HI[acc], t2);
+            gen_move_high32_tl(cpu_HI[acc], t2);
         }
         break;
     case OPC_MADDU:
@@ -3358,7 +3358,7 @@  static void gen_muldiv(DisasContext *ctx, uint32_t opc,
             tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
             tcg_gen_add_i64(t2, t2, t3);
             gen_move_low32_tl(cpu_LO[acc], t2);
-            gen_move_high32(cpu_HI[acc], t2);
+            gen_move_high32_tl(cpu_HI[acc], t2);
         }
         break;
     case OPC_MSUB:
@@ -3372,7 +3372,7 @@  static void gen_muldiv(DisasContext *ctx, uint32_t opc,
             tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
             tcg_gen_sub_i64(t2, t3, t2);
             gen_move_low32_tl(cpu_LO[acc], t2);
-            gen_move_high32(cpu_HI[acc], t2);
+            gen_move_high32_tl(cpu_HI[acc], t2);
         }
         break;
     case OPC_MSUBU:
@@ -3388,7 +3388,7 @@  static void gen_muldiv(DisasContext *ctx, uint32_t opc,
             tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
             tcg_gen_sub_i64(t2, t3, t2);
             gen_move_low32_tl(cpu_LO[acc], t2);
-            gen_move_high32(cpu_HI[acc], t2);
+            gen_move_high32_tl(cpu_HI[acc], t2);
         }
         break;
     default:
@@ -3483,7 +3483,7 @@  static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,
             tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
             tcg_gen_add_i64(t2, t2, t3);
             gen_move_low32_tl(cpu_LO[acc], t2);
-            gen_move_high32(cpu_HI[acc], t2);
+            gen_move_high32_tl(cpu_HI[acc], t2);
             if (rd) {
                 gen_move_low32_tl(cpu_gpr[rd], t2);
             }
@@ -3505,7 +3505,7 @@  static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,
             tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
             tcg_gen_add_i64(t2, t2, t3);
             gen_move_low32_tl(cpu_LO[acc], t2);
-            gen_move_high32(cpu_HI[acc], t2);
+            gen_move_high32_tl(cpu_HI[acc], t2);
             if (rd) {
                 gen_move_low32_tl(cpu_gpr[rd], t2);
             }
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
index 5a4a64f3609..b78381bcf54 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -1817,7 +1817,7 @@  static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
                 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
                 tcg_gen_add_i64(t2, t2, t3);
                 gen_move_low32_tl(cpu_LO[acc], t2);
-                gen_move_high32(cpu_HI[acc], t2);
+                gen_move_high32_tl(cpu_HI[acc], t2);
             }
             break;
         case NM_MULT:
@@ -1872,7 +1872,7 @@  static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
                 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
                 tcg_gen_add_i64(t2, t2, t3);
                 gen_move_low32_tl(cpu_LO[acc], t2);
-                gen_move_high32(cpu_HI[acc], t2);
+                gen_move_high32_tl(cpu_HI[acc], t2);
             }
             break;
         case NM_MULTU:
@@ -1933,7 +1933,7 @@  static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
                 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
                 tcg_gen_sub_i64(t2, t3, t2);
                 gen_move_low32_tl(cpu_LO[acc], t2);
-                gen_move_high32(cpu_HI[acc], t2);
+                gen_move_high32_tl(cpu_HI[acc], t2);
             }
             break;
         case NM_EXTRV_RS_W:
@@ -1974,7 +1974,7 @@  static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
                 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
                 tcg_gen_sub_i64(t2, t3, t2);
                 gen_move_low32_tl(cpu_LO[acc], t2);
-                gen_move_high32(cpu_HI[acc], t2);
+                gen_move_high32_tl(cpu_HI[acc], t2);
             }
             break;
         case NM_EXTRV_S_H: