| Message ID | 20241126131546.66145-8-philmd@linaro.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | target/mips: Simplify some target_ulong registers to 32-bit | expand |
On 11/26/24 07:15, Philippe Mathieu-Daudé wrote: > Similarly to the gen_load_gpr_tl() helper which loads a > target-wide TCG register from the CPU generic purpose > registers, add a helper to load 32-bit TCG register. > > Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org> > --- Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index 9517e18eef9..e15d631ad2a 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -156,6 +156,7 @@ void gen_base_offset_addr_tl(DisasContext *ctx, TCGv addr, int base, int offset) void gen_move_low32_tl(TCGv ret, TCGv_i64 arg); void gen_move_high32_tl(TCGv ret, TCGv_i64 arg); void gen_load_gpr_tl(TCGv t, int reg); +void gen_load_gpr_i32(TCGv_i32 t, int reg); void gen_store_gpr_tl(TCGv t, int reg); #if defined(TARGET_MIPS64) void gen_load_gpr_hi(TCGv_i64 t, int reg); diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index ad688b9b23d..d7c83c863d5 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1198,6 +1198,16 @@ void gen_load_gpr_tl(TCGv t, int reg) } } +void gen_load_gpr_i32(TCGv_i32 t, int reg) +{ + assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr)); + if (reg == 0) { + tcg_gen_movi_i32(t, 0); + } else { + tcg_gen_trunc_tl_i32(t, cpu_gpr[reg]); + } +} + void gen_store_gpr_tl(TCGv t, int reg) { assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr));
Similarly to the gen_load_gpr_tl() helper which loads a target-wide TCG register from the CPU generic purpose registers, add a helper to load 32-bit TCG register. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- target/mips/tcg/translate.h | 1 + target/mips/tcg/translate.c | 10 ++++++++++ 2 files changed, 11 insertions(+)