| Message ID | 20241122164636.2944180-1-james.clark@linaro.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: Fix usage of new shifted MDCR_EL2 values | expand |
On Fri, 22 Nov 2024 16:46:35 +0000, James Clark <james.clark@linaro.org> wrote: > > Since the linked fixes commit, these masks are already shifted so remove > the shifts. One issue that this fixes is SPE and TRBE not being > available anymore: > > arm_spe_pmu arm,spe-v1: profiling buffer owned by higher exception level > > Fixes: 641630313e9c ("arm64: sysreg: Migrate MDCR_EL2 definition to table") > Signed-off-by: James Clark <james.clark@linaro.org> Huh, well spotted. This is doubleplusungood. Thankfully, the KVM/arm64 tree hasn't reached Linus yet, but this needs quick fixing. Acked-by: Marc Zyngier <maz@kernel.org> M.
+cc Paolo Ugh, sorry for the mess + thanks for the fix James. Paolo -- would you be able to apply this patch directly to your tree? This really should go in ASAP. Otherwise, I'll grab it + send another pull. On Fri, Nov 22, 2024 at 04:46:35PM +0000, James Clark wrote: > Since the linked fixes commit, these masks are already shifted so remove > the shifts. One issue that this fixes is SPE and TRBE not being > available anymore: > > arm_spe_pmu arm,spe-v1: profiling buffer owned by higher exception level > > Fixes: 641630313e9c ("arm64: sysreg: Migrate MDCR_EL2 definition to table") > Signed-off-by: James Clark <james.clark@linaro.org> Acked-by: Oliver Upton <oliver.upton@linux.dev>
On Fri, 22 Nov 2024 16:46:35 +0000, James Clark wrote: > Since the linked fixes commit, these masks are already shifted so remove > the shifts. One issue that this fixes is SPE and TRBE not being > available anymore: > > arm_spe_pmu arm,spe-v1: profiling buffer owned by higher exception level > > > [...] Applied to fixes, thanks! [1/1] arm64: Fix usage of new shifted MDCR_EL2 values https://git.kernel.org/kvmarm/kvmarm/c/d798bc6f3c17 -- Best, Oliver
diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h index 4cd41464be3f..f134907d3c08 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -79,7 +79,7 @@ 1 << PMSCR_EL2_PA_SHIFT) msr_s SYS_PMSCR_EL2, x0 // addresses and physical counter .Lskip_spe_el2_\@: - mov x0, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT) + mov x0, #MDCR_EL2_E2PB_MASK orr x2, x2, x0 // If we don't have VHE, then // use EL1&0 translation. @@ -92,7 +92,7 @@ and x0, x0, TRBIDR_EL1_P cbnz x0, .Lskip_trace_\@ // If TRBE is available at EL2 - mov x0, #(MDCR_EL2_E2TB_MASK << MDCR_EL2_E2TB_SHIFT) + mov x0, #MDCR_EL2_E2TB_MASK orr x2, x2, x0 // allow the EL1&0 translation // to own it. diff --git a/arch/arm64/kernel/hyp-stub.S b/arch/arm64/kernel/hyp-stub.S index 65f76064c86b..ae990da1eae5 100644 --- a/arch/arm64/kernel/hyp-stub.S +++ b/arch/arm64/kernel/hyp-stub.S @@ -114,8 +114,8 @@ SYM_CODE_START_LOCAL(__finalise_el2) // Use EL2 translations for SPE & TRBE and disable access from EL1 mrs x0, mdcr_el2 - bic x0, x0, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT) - bic x0, x0, #(MDCR_EL2_E2TB_MASK << MDCR_EL2_E2TB_SHIFT) + bic x0, x0, #MDCR_EL2_E2PB_MASK + bic x0, x0, #MDCR_EL2_E2TB_MASK msr mdcr_el2, x0 // Transfer the MM state from EL1 to EL2 diff --git a/arch/arm64/kvm/hyp/nvhe/pkvm.c b/arch/arm64/kvm/hyp/nvhe/pkvm.c index 01616c39a810..071993c16de8 100644 --- a/arch/arm64/kvm/hyp/nvhe/pkvm.c +++ b/arch/arm64/kvm/hyp/nvhe/pkvm.c @@ -126,7 +126,7 @@ static void pvm_init_traps_aa64dfr0(struct kvm_vcpu *vcpu) /* Trap SPE */ if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer), feature_ids)) { mdcr_set |= MDCR_EL2_TPMS; - mdcr_clear |= MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT; + mdcr_clear |= MDCR_EL2_E2PB_MASK; } /* Trap Trace Filter */ @@ -143,7 +143,7 @@ static void pvm_init_traps_aa64dfr0(struct kvm_vcpu *vcpu) /* Trap External Trace */ if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_ExtTrcBuff), feature_ids)) - mdcr_clear |= MDCR_EL2_E2TB_MASK << MDCR_EL2_E2TB_SHIFT; + mdcr_clear |= MDCR_EL2_E2TB_MASK; vcpu->arch.mdcr_el2 |= mdcr_set; vcpu->arch.mdcr_el2 &= ~mdcr_clear;
Since the linked fixes commit, these masks are already shifted so remove the shifts. One issue that this fixes is SPE and TRBE not being available anymore: arm_spe_pmu arm,spe-v1: profiling buffer owned by higher exception level Fixes: 641630313e9c ("arm64: sysreg: Migrate MDCR_EL2 definition to table") Signed-off-by: James Clark <james.clark@linaro.org> --- arch/arm64/include/asm/el2_setup.h | 4 ++-- arch/arm64/kernel/hyp-stub.S | 4 ++-- arch/arm64/kvm/hyp/nvhe/pkvm.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-)