| Message ID | 20241126153955.477569-3-mark.rutland@arm.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add support for FEAT_FPMR and FEAT_GCS | expand |
On Tue, Nov 26, 2024 at 03:39:54PM +0000, Mark Rutland wrote: > FEAT_FPMR adds the FPMR register. Acceses to FPMR (whether direct or > indirect) trap to EL3 unless SCR_EL3.EnFPM is set, and so boot-wrapper > support is necessary. Reviewed-by: Mark Brown <broonie@kernel.org>
diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h index 6fa11da..3ef58f3 100644 --- a/arch/aarch64/include/asm/cpu.h +++ b/arch/aarch64/include/asm/cpu.h @@ -68,6 +68,7 @@ #define SCR_EL3_SCTLR2En BIT(44) #define SCR_EL3_PIEN BIT(45) #define SCR_EL3_D128En BIT(47) +#define SCR_EL3_EnFPM BIT(50) #define VTCR_EL2_MSA BIT(31) @@ -116,6 +117,9 @@ #define ID_AA64PFR1_EL1_CSV2_frac BITS(35, 32) #define ID_AA64PFR1_EL1_THE BITS(51, 48) +#define ID_AA64PFR2_EL1 s3_0_c0_c4_2 +#define ID_AA64PFR2_EL1_FPMR BITS(35, 32) + #define ID_AA64SMFR0_EL1 s3_0_c0_c4_5 #define ID_AA64SMFR0_EL1_FA64 BIT(63) diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c index da036bb..1f38516 100644 --- a/arch/aarch64/init.c +++ b/arch/aarch64/init.c @@ -124,6 +124,9 @@ static void cpu_init_el3(void) if (mrs_field(ID_AA64PFR1_EL1, THE)) scr |= SCR_EL3_RCWMASKEn; + if (mrs_field(ID_AA64PFR2_EL1, FPMR)) + scr |= SCR_EL3_EnFPM; + msr(SCR_EL3, scr); msr(CPTR_EL3, cptr);
FEAT_FPMR adds the FPMR register. Acceses to FPMR (whether direct or indirect) trap to EL3 unless SCR_EL3.EnFPM is set, and so boot-wrapper support is necessary. Support for FEAT_FPMR was added to Linux in v6.8 without any boot-wrapper support. Consequently when FPMR is enabled in a model, the kernel will hang when attempting to write to the FPMR (e.g. when entering userspace for the first time). Add boot-wrapper support for FEAT_FPMR. As FPMR is not described in the latest ARM ARM (ARM DDI 0487K.a), the relevant definitions are taken from the 2024-09 release of the "Arm Architecture Registers" document, ARM DDI 0601 (ID092424), which can be found at: https://developer.arm.com/documentation/ddi0601/2024-09/?lang=en The ID_AA64PFR2_EL1 ID register has existed as reserved RES0 space since ARMv8.0 but only recently gained a name, and so older assemblers may not be able to encode ID_AA64PFR2_EL1 directly. Thus we need an explicit definition of the sysreg encoding to support these assemblers. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Mark Brown <broonie@kernel.org> --- arch/aarch64/include/asm/cpu.h | 4 ++++ arch/aarch64/init.c | 3 +++ 2 files changed, 7 insertions(+)