| Message ID | 20241126131736.465111-2-heiko@sntech.de (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | MIPI DSI phy for rk3588 | expand |
Hi, On Tue, Nov 26, 2024 at 02:17:34PM +0100, Heiko Stuebner wrote: > From: Heiko Stuebner <heiko.stuebner@cherry.de> > > Add dt-binding schema for the MIPI C-/D-PHY found on > Rockchip RK3588 SoCs. > > Tested-by: Daniel Semkowicz <dse@thaumatec.com> > Tested-by: Sebastian Reichel <sebastian.reichel@collabora.com> > Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de> > --- Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com> -- Sebastian > .../phy/rockchip,rk3588-mipi-dcphy.yaml | 87 +++++++++++++++++++ > 1 file changed, 87 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/rockchip,rk3588-mipi-dcphy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/rockchip,rk3588-mipi-dcphy.yaml b/Documentation/devicetree/bindings/phy/rockchip,rk3588-mipi-dcphy.yaml > new file mode 100644 > index 000000000000..c8ff5ba22a86 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/rockchip,rk3588-mipi-dcphy.yaml > @@ -0,0 +1,87 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/rockchip,rk3588-mipi-dcphy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Rockchip MIPI D-/C-PHY with Samsung IP block > + > +maintainers: > + - Guochun Huang <hero.huang@rock-chips.com> > + - Heiko Stuebner <heiko@sntech.de> > + > +properties: > + compatible: > + enum: > + - rockchip,rk3576-mipi-dcphy > + - rockchip,rk3588-mipi-dcphy > + > + reg: > + maxItems: 1 > + > + "#phy-cells": > + const: 1 > + description: | > + Argument is mode to operate in. Supported modes are: > + - PHY_TYPE_DPHY > + - PHY_TYPE_CPHY > + See include/dt-bindings/phy/phy.h for constants. > + > + clocks: > + maxItems: 2 > + > + clock-names: > + items: > + - const: pclk > + - const: ref > + > + resets: > + maxItems: 4 > + > + reset-names: > + items: > + - const: m_phy > + - const: apb > + - const: grf > + - const: s_phy > + > + rockchip,grf: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + Phandle to the syscon managing the 'mipi dcphy general register files'. > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - resets > + - reset-names > + - "#phy-cells" > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/rockchip,rk3588-cru.h> > + #include <dt-bindings/reset/rockchip,rk3588-cru.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + phy@feda0000 { > + compatible = "rockchip,rk3588-mipi-dcphy"; > + reg = <0x0 0xfeda0000 0x0 0x10000>; > + clocks = <&cru PCLK_MIPI_DCPHY0>, > + <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>; > + clock-names = "pclk", "ref"; > + resets = <&cru SRST_M_MIPI_DCPHY0>, > + <&cru SRST_P_MIPI_DCPHY0>, > + <&cru SRST_P_MIPI_DCPHY0_GRF>, > + <&cru SRST_S_MIPI_DCPHY0>; > + reset-names = "m_phy", "apb", "grf", "s_phy"; > + rockchip,grf = <&mipidcphy0_grf>; > + #phy-cells = <1>; > + }; > + }; > -- > 2.45.2 >
On Tue, Nov 26, 2024 at 02:17:34PM +0100, Heiko Stuebner wrote: > From: Heiko Stuebner <heiko.stuebner@cherry.de> > > Add dt-binding schema for the MIPI C-/D-PHY found on > Rockchip RK3588 SoCs. > > Tested-by: Daniel Semkowicz <dse@thaumatec.com> > Tested-by: Sebastian Reichel <sebastian.reichel@collabora.com> > Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de> > --- > .../phy/rockchip,rk3588-mipi-dcphy.yaml | 87 +++++++++++++++++++ > 1 file changed, 87 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/rockchip,rk3588-mipi-dcphy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/rockchip,rk3588-mipi-dcphy.yaml b/Documentation/devicetree/bindings/phy/rockchip,rk3588-mipi-dcphy.yaml > new file mode 100644 > index 000000000000..c8ff5ba22a86 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/rockchip,rk3588-mipi-dcphy.yaml > @@ -0,0 +1,87 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/rockchip,rk3588-mipi-dcphy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Rockchip MIPI D-/C-PHY with Samsung IP block > + > +maintainers: > + - Guochun Huang <hero.huang@rock-chips.com> > + - Heiko Stuebner <heiko@sntech.de> > + > +properties: > + compatible: > + enum: > + - rockchip,rk3576-mipi-dcphy > + - rockchip,rk3588-mipi-dcphy How many phys do each of these SoCs have?
Hey Conor, Am Dienstag, 26. November 2024, 18:44:14 CET schrieb Conor Dooley: > On Tue, Nov 26, 2024 at 02:17:34PM +0100, Heiko Stuebner wrote: > > From: Heiko Stuebner <heiko.stuebner@cherry.de> > > > > Add dt-binding schema for the MIPI C-/D-PHY found on > > Rockchip RK3588 SoCs. > > > > Tested-by: Daniel Semkowicz <dse@thaumatec.com> > > Tested-by: Sebastian Reichel <sebastian.reichel@collabora.com> > > Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de> > > --- > > .../phy/rockchip,rk3588-mipi-dcphy.yaml | 87 +++++++++++++++++++ > > 1 file changed, 87 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/phy/rockchip,rk3588-mipi-dcphy.yaml > > > > diff --git a/Documentation/devicetree/bindings/phy/rockchip,rk3588-mipi-dcphy.yaml b/Documentation/devicetree/bindings/phy/rockchip,rk3588-mipi-dcphy.yaml > > new file mode 100644 > > index 000000000000..c8ff5ba22a86 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/phy/rockchip,rk3588-mipi-dcphy.yaml > > @@ -0,0 +1,87 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/phy/rockchip,rk3588-mipi-dcphy.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Rockchip MIPI D-/C-PHY with Samsung IP block > > + > > +maintainers: > > + - Guochun Huang <hero.huang@rock-chips.com> > > + - Heiko Stuebner <heiko@sntech.de> > > + > > +properties: > > + compatible: > > + enum: > > + - rockchip,rk3576-mipi-dcphy > > + - rockchip,rk3588-mipi-dcphy > > How many phys do each of these SoCs have? - rk3588 has two - each with a separate GRF for additional settings [0] - rk3576 has one Heiko [0] https://lore.kernel.org/lkml/D5F5C1RWVHG5.TSHPO29TXYEF@cknow.org/T/ The register layout in each GRF area is identical, but each DC-PHY gets its own separate GRF io-mem block.
diff --git a/Documentation/devicetree/bindings/phy/rockchip,rk3588-mipi-dcphy.yaml b/Documentation/devicetree/bindings/phy/rockchip,rk3588-mipi-dcphy.yaml new file mode 100644 index 000000000000..c8ff5ba22a86 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/rockchip,rk3588-mipi-dcphy.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/rockchip,rk3588-mipi-dcphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip MIPI D-/C-PHY with Samsung IP block + +maintainers: + - Guochun Huang <hero.huang@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +properties: + compatible: + enum: + - rockchip,rk3576-mipi-dcphy + - rockchip,rk3588-mipi-dcphy + + reg: + maxItems: 1 + + "#phy-cells": + const: 1 + description: | + Argument is mode to operate in. Supported modes are: + - PHY_TYPE_DPHY + - PHY_TYPE_CPHY + See include/dt-bindings/phy/phy.h for constants. + + clocks: + maxItems: 2 + + clock-names: + items: + - const: pclk + - const: ref + + resets: + maxItems: 4 + + reset-names: + items: + - const: m_phy + - const: apb + - const: grf + - const: s_phy + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the 'mipi dcphy general register files'. + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/rockchip,rk3588-cru.h> + #include <dt-bindings/reset/rockchip,rk3588-cru.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + phy@feda0000 { + compatible = "rockchip,rk3588-mipi-dcphy"; + reg = <0x0 0xfeda0000 0x0 0x10000>; + clocks = <&cru PCLK_MIPI_DCPHY0>, + <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>; + clock-names = "pclk", "ref"; + resets = <&cru SRST_M_MIPI_DCPHY0>, + <&cru SRST_P_MIPI_DCPHY0>, + <&cru SRST_P_MIPI_DCPHY0_GRF>, + <&cru SRST_S_MIPI_DCPHY0>; + reset-names = "m_phy", "apb", "grf", "s_phy"; + rockchip,grf = <&mipidcphy0_grf>; + #phy-cells = <1>; + }; + };