| Message ID | 20241127-mdss_qcs8300-v1-1-29b2c3ee95b8@quicinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Display enablement changes for Qualcomm QCS8300 platform | expand |
On 27/11/2024 08:05, Yongxing Mou wrote: > Document the MDSS hardware found on the Qualcomm QCS8300 platform. > > Signed-off-by: Yongxing Mou <quic_yongmou@quicinc.com> Will fail testing, so only limited review. > +examples: > + - | > + #include <dt-bindings/interconnect/qcom,icc.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/clock/qcom,qcs8300-gcc.h> > + #include <dt-bindings/clock/qcom,sa8775p-dispcc.h> > + #include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h> > + #include <dt-bindings/power/qcom,rpmhpd.h> > + #include <dt-bindings/power/qcom-rpmpd.h> > + > + mdss: display-subsystem@ae00000 { > + compatible = "qcom,qcs8300-mdss"; > + reg = <0 0x0ae00000 0 0x1000>; > + reg-names = "mdss"; > + > + interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, > + <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ACTIVE_ONLY > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY > + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; > + interconnect-names = "mdp0-mem", > + "mdp1-mem", > + "cpu-cfg"; > + > + power-domains = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>; > + > + clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>, > + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>; > + > + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + #interrupt-cells = <1>; > + > + iommus = <&apps_smmu 0x1000 0x402>; > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + status = "disabled"; No, your code cannot be disabled. > + > + mdss_mdp: display-controller@ae01000 { > + compatible = "qcom,qcs8300-dpu"; > + reg = <0 0x0ae01000 0 0x8f000>, > + <0 0x0aeb0000 0 0x2008>; > + reg-names = "mdp", "vbif"; > + > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, > + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, > + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, > + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>, > + <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; > + clock-names = "bus", > + "iface", > + "lut", > + "core", > + "vsync"; > + > + assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; > + assigned-clock-rates = <19200000>; > + operating-points-v2 = <&mdp_opp_table>; > + power-domains = <&rpmhpd RPMHPD_MMCX>; > + > + interrupt-parent = <&mdss>; > + interrupts = <0>; > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + port@0 { > + reg = <0>; > + dpu_intf0_out: endpoint { > + remote-endpoint = <&mdss_dp0_in>; > + }; > + }; > + }; > + > + mdp_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-375000000 { > + opp-hz = /bits/ 64 <375000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-500000000 { > + opp-hz = /bits/ 64 <500000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + > + opp-575000000 { > + opp-hz = /bits/ 64 <575000000>; > + required-opps = <&rpmhpd_opp_turbo>; > + }; > + > + opp-650000000 { > + opp-hz = /bits/ 64 <650000000>; > + required-opps = <&rpmhpd_opp_turbo_l1>; > + }; > + }; > + }; > + > + mdss_dp0: displayport-controller@af54000 { > + compatible = "qcom,qcs8300-dp"; > + > + pinctrl-0 = <&dp_hot_plug_det>; > + pinctrl-names = "default"; > + > + reg = <0 0xaf54000 0 0x104>, > + <0 0xaf54200 0 0x0c0>, > + <0 0xaf55000 0 0x770>, > + <0 0xaf56000 0 0x09c>; > + > + interrupt-parent = <&mdss>; > + interrupts = <12>; > + clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, > + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, Messed alignment in multiple places. > + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, > + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, > + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; > + clock-names = "core_iface", > + "core_aux", > + "ctrl_link", > + "ctrl_link_iface", > + "stream_pixel"; > + assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, > + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; > + assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; > + phys = <&mdss_edp_phy>; > + phy-names = "dp"; > + operating-points-v2 = <&dp_opp_table>; > + power-domains = <&rpmhpd RPMHPD_MMCX>; > + > + #sound-dai-cells = <0>; > + status = "disabled"; No, your code cannot be disabled. > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + mdss_dp0_in: endpoint { > + remote-endpoint = <&dpu_intf0_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + mdss_dp_out: endpoint { }; > + }; > + }; > + > + dp_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-160000000 { > + opp-hz = /bits/ 64 <160000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-270000000 { > + opp-hz = /bits/ 64 <270000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-540000000 { > + opp-hz = /bits/ 64 <540000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-810000000 { > + opp-hz = /bits/ 64 <810000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + Drop stray blank lines. > + }; > +... > Best regards, Krzysztof
On 2024/11/27 15:15, Krzysztof Kozlowski wrote: > On 27/11/2024 08:05, Yongxing Mou wrote: >> Document the MDSS hardware found on the Qualcomm QCS8300 platform. >> >> Signed-off-by: Yongxing Mou <quic_yongmou@quicinc.com> > > > Will fail testing, so only limited review. > Thanks for reviewing,will fix it in next patchset. >> +examples: >> + - | >> + #include <dt-bindings/interconnect/qcom,icc.h> >> + #include <dt-bindings/interrupt-controller/arm-gic.h> >> + #include <dt-bindings/clock/qcom,qcs8300-gcc.h> >> + #include <dt-bindings/clock/qcom,sa8775p-dispcc.h> >> + #include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h> >> + #include <dt-bindings/power/qcom,rpmhpd.h> >> + #include <dt-bindings/power/qcom-rpmpd.h> >> + >> + mdss: display-subsystem@ae00000 { >> + compatible = "qcom,qcs8300-mdss"; >> + reg = <0 0x0ae00000 0 0x1000>; >> + reg-names = "mdss"; >> + >> + interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, >> + <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ACTIVE_ONLY >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY >> + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; >> + interconnect-names = "mdp0-mem", >> + "mdp1-mem", >> + "cpu-cfg"; >> + >> + power-domains = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>; >> + >> + clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, >> + <&gcc GCC_DISP_HF_AXI_CLK>, >> + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>; >> + >> + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-controller; >> + #interrupt-cells = <1>; >> + >> + iommus = <&apps_smmu 0x1000 0x402>; >> + >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + >> + status = "disabled"; > > No, your code cannot be disabled. > Thanks, will remove it. >> + >> + mdss_mdp: display-controller@ae01000 { >> + compatible = "qcom,qcs8300-dpu"; >> + reg = <0 0x0ae01000 0 0x8f000>, >> + <0 0x0aeb0000 0 0x2008>; >> + reg-names = "mdp", "vbif"; >> + >> + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, >> + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, >> + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, >> + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>, >> + <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; >> + clock-names = "bus", >> + "iface", >> + "lut", >> + "core", >> + "vsync"; >> + >> + assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; >> + assigned-clock-rates = <19200000>; >> + operating-points-v2 = <&mdp_opp_table>; >> + power-domains = <&rpmhpd RPMHPD_MMCX>; >> + >> + interrupt-parent = <&mdss>; >> + interrupts = <0>; >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + port@0 { >> + reg = <0>; >> + dpu_intf0_out: endpoint { >> + remote-endpoint = <&mdss_dp0_in>; >> + }; >> + }; >> + }; >> + >> + mdp_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-375000000 { >> + opp-hz = /bits/ 64 <375000000>; >> + required-opps = <&rpmhpd_opp_svs_l1>; >> + }; >> + >> + opp-500000000 { >> + opp-hz = /bits/ 64 <500000000>; >> + required-opps = <&rpmhpd_opp_nom>; >> + }; >> + >> + opp-575000000 { >> + opp-hz = /bits/ 64 <575000000>; >> + required-opps = <&rpmhpd_opp_turbo>; >> + }; >> + >> + opp-650000000 { >> + opp-hz = /bits/ 64 <650000000>; >> + required-opps = <&rpmhpd_opp_turbo_l1>; >> + }; >> + }; >> + }; >> + >> + mdss_dp0: displayport-controller@af54000 { >> + compatible = "qcom,qcs8300-dp"; >> + >> + pinctrl-0 = <&dp_hot_plug_det>; >> + pinctrl-names = "default"; >> + >> + reg = <0 0xaf54000 0 0x104>, >> + <0 0xaf54200 0 0x0c0>, >> + <0 0xaf55000 0 0x770>, >> + <0 0xaf56000 0 0x09c>; >> + >> + interrupt-parent = <&mdss>; >> + interrupts = <12>; >> + clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, >> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, > > Messed alignment in multiple places. > Thanks, will fix it in next patchset. >> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, >> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, >> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; >> + clock-names = "core_iface", >> + "core_aux", >> + "ctrl_link", >> + "ctrl_link_iface", >> + "stream_pixel"; >> + assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, >> + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; >> + assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; >> + phys = <&mdss_edp_phy>; >> + phy-names = "dp"; >> + operating-points-v2 = <&dp_opp_table>; >> + power-domains = <&rpmhpd RPMHPD_MMCX>; >> + >> + #sound-dai-cells = <0>; >> + status = "disabled"; > > No, your code cannot be disabled. > Got it. will remove it. >> + >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + reg = <0>; >> + mdss_dp0_in: endpoint { >> + remote-endpoint = <&dpu_intf0_out>; >> + }; >> + }; >> + >> + port@1 { >> + reg = <1>; >> + mdss_dp_out: endpoint { }; >> + }; >> + }; >> + >> + dp_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-160000000 { >> + opp-hz = /bits/ 64 <160000000>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-270000000 { >> + opp-hz = /bits/ 64 <270000000>; >> + required-opps = <&rpmhpd_opp_svs>; >> + }; >> + >> + opp-540000000 { >> + opp-hz = /bits/ 64 <540000000>; >> + required-opps = <&rpmhpd_opp_svs_l1>; >> + }; >> + >> + opp-810000000 { >> + opp-hz = /bits/ 64 <810000000>; >> + required-opps = <&rpmhpd_opp_nom>; >> + }; >> + }; >> + > > Drop stray blank lines. > Got it.will fix this issue,there should be a '}'. >> + }; >> +... >> > > > Best regards, > Krzysztof
On Wed, 27 Nov 2024 15:05:01 +0800, Yongxing Mou wrote: > Document the MDSS hardware found on the Qualcomm QCS8300 platform. > > Signed-off-by: Yongxing Mou <quic_yongmou@quicinc.com> > --- > .../bindings/display/msm/qcom,qcs8300-mdss.yaml | 239 +++++++++++++++++++++ > 1 file changed, 239 insertions(+) > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: dtschema/dtc warnings/errors: Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.example.dts:26:18: fatal error: dt-bindings/clock/qcom,qcs8300-gcc.h: No such file or directory 26 | #include <dt-bindings/clock/qcom,qcs8300-gcc.h> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ compilation terminated. make[2]: *** [scripts/Makefile.dtbs:129: Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.example.dtb] Error 1 make[2]: *** Waiting for unfinished jobs.... make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1442: dt_binding_check] Error 2 make: *** [Makefile:224: __sub-make] Error 2 doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20241127-mdss_qcs8300-v1-1-29b2c3ee95b8@quicinc.com The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
On 2024/11/27 16:21, Rob Herring (Arm) wrote: > > On Wed, 27 Nov 2024 15:05:01 +0800, Yongxing Mou wrote: >> Document the MDSS hardware found on the Qualcomm QCS8300 platform. >> >> Signed-off-by: Yongxing Mou <quic_yongmou@quicinc.com> >> --- >> .../bindings/display/msm/qcom,qcs8300-mdss.yaml | 239 +++++++++++++++++++++ >> 1 file changed, 239 insertions(+) >> > > My bot found errors running 'make dt_binding_check' on your patch: > > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.example.dts:26:18: fatal error: dt-bindings/clock/qcom,qcs8300-gcc.h: No such file or directory > 26 | #include <dt-bindings/clock/qcom,qcs8300-gcc.h> > | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > compilation terminated. > make[2]: *** [scripts/Makefile.dtbs:129: Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.example.dtb] Error 1 > make[2]: *** Waiting for unfinished jobs.... > make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1442: dt_binding_check] Error 2 > make: *** [Makefile:224: __sub-make] Error 2 > > doc reference errors (make refcheckdocs): > > See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20241127-mdss_qcs8300-v1-1-29b2c3ee95b8@quicinc.com > > The base for the series is generally the latest rc1. A different dependency > should be noted in *this* patch. > > If you already ran 'make dt_binding_check' and didn't see the above > error(s), then make sure 'yamllint' is installed and dt-schema is up to > date: > > pip3 install dtschema --upgrade > > Please check and re-submit after running the above command yourself. Note > that DT_SCHEMA_FILES can be set to your schema file to speed up checking > your schema. However, it must be unset to test all examples with your schema. > Thank you for your checking. I rechecked this file and indeed found some issues. I will fix them in the next patchset. But i did not see issues related to this header file in local. Maybe it is dependency or tool issues. I will and update tool and recheck this issue and fix it in the next patchset.
On 27/11/2024 12:02, Yongxing Mou wrote: >> >> doc reference errors (make refcheckdocs): >> >> See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20241127-mdss_qcs8300-v1-1-29b2c3ee95b8@quicinc.com >> >> The base for the series is generally the latest rc1. A different dependency >> should be noted in *this* patch. >> >> If you already ran 'make dt_binding_check' and didn't see the above >> error(s), then make sure 'yamllint' is installed and dt-schema is up to >> date: >> >> pip3 install dtschema --upgrade >> >> Please check and re-submit after running the above command yourself. Note >> that DT_SCHEMA_FILES can be set to your schema file to speed up checking >> your schema. However, it must be unset to test all examples with your schema. >> > Thank you for your checking. I rechecked this file and indeed found some > issues. I will fix them in the next patchset. But i did not see issues > related to this header file in local. Maybe it is dependency or tool > issues. I will and update tool and recheck this issue and fix it in the > next patchset. > Read the instruction carefully, including statement about base. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml new file mode 100644 index 0000000000000000000000000000000000000000..87d6599d30b2b7b689eb31d3690c0de511aecb95 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml @@ -0,0 +1,239 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,qcs8300-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. QCS8300 Display MDSS + +maintainers: + - Yongxing Mou <quic_yongmou@quicinc.com> + +description: + QCS8300 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like + DPU display controller, DP interfaces and EDP etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,qcs8300-mdss + + clocks: + items: + - description: Display AHB + - description: Display hf AXI + - description: Display core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 3 + + interconnect-names: + maxItems: 3 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,qcs8300-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + items: + - const: qcom,qcs8300-dp + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interconnect/qcom,icc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/qcom,qcs8300-gcc.h> + #include <dt-bindings/clock/qcom,sa8775p-dispcc.h> + #include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h> + #include <dt-bindings/power/qcom,rpmhpd.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + mdss: display-subsystem@ae00000 { + compatible = "qcom,qcs8300-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "mdp1-mem", + "cpu-cfg"; + + power-domains = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>; + + clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>; + + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x1000 0x402>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,qcs8300-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-575000000 { + opp-hz = /bits/ 64 <575000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + required-opps = <&rpmhpd_opp_turbo_l1>; + }; + }; + }; + + mdss_dp0: displayport-controller@af54000 { + compatible = "qcom,qcs8300-dp"; + + pinctrl-0 = <&dp_hot_plug_det>; + pinctrl-names = "default"; + + reg = <0 0xaf54000 0 0x104>, + <0 0xaf54200 0 0x0c0>, + <0 0xaf55000 0 0x770>, + <0 0xaf56000 0 0x09c>; + + interrupt-parent = <&mdss>; + interrupts = <12>; + clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; + phys = <&mdss_edp_phy>; + phy-names = "dp"; + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + #sound-dai-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dp0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dp_out: endpoint { }; + }; + }; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + + }; +...
Document the MDSS hardware found on the Qualcomm QCS8300 platform. Signed-off-by: Yongxing Mou <quic_yongmou@quicinc.com> --- .../bindings/display/msm/qcom,qcs8300-mdss.yaml | 239 +++++++++++++++++++++ 1 file changed, 239 insertions(+)