Message ID | 20241203034932.25185-7-fea.wang@sifive.com (mailing list archive) |
---|---|
State | New |
Headers | show |
Series | Introduce svukte ISA extension | expand |
On Tue, Dec 3, 2024 at 12:39 PM Fea.Wang <fea.wang@sifive.com> wrote: > > The spec explicitly says svukte doesn't support RV32. So check that it > is not enabled in RV32. > > Signed-off-by: Fea.Wang <fea.wang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/tcg/tcg-cpu.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index c62c221696..3b99c8c9e3 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -652,6 +652,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) > return; > } > > + if (mcc->misa_mxl_max == MXL_RV32 && cpu->cfg.ext_svukte) { > + error_setg(errp, "svukte is not supported for RV32"); > + return; > + } > + > /* > * Disable isa extensions based on priv spec after we > * validated and set everything we need. > -- > 2.34.1 > >
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index c62c221696..3b99c8c9e3 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -652,6 +652,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) return; } + if (mcc->misa_mxl_max == MXL_RV32 && cpu->cfg.ext_svukte) { + error_setg(errp, "svukte is not supported for RV32"); + return; + } + /* * Disable isa extensions based on priv spec after we * validated and set everything we need.
The spec explicitly says svukte doesn't support RV32. So check that it is not enabled in RV32. Signed-off-by: Fea.Wang <fea.wang@sifive.com> --- target/riscv/tcg/tcg-cpu.c | 5 +++++ 1 file changed, 5 insertions(+)