| Message ID | 20241203095920.505018-1-dpiliaiev@igalia.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Expose UCHE_TRAP_BASE value via uapi | expand |
On 12/3/24 14:34, Dmitry Baryshkov wrote: > On Tue, Dec 03, 2024 at 02:09:59PM +0100, Danylo wrote: >> >> >> On 12/3/24 13:52, Dmitry Baryshkov wrote: >>> On Tue, Dec 03, 2024 at 10:59:20AM +0100, Danylo Piliaiev wrote: >>>> This adds MSM_PARAM_UCHE_TRAP_BASE that will be used by Mesa >>>> implementation for VK_KHR_shader_clock and GL_ARB_shader_clock. >>> Could you please spend more words, describing what it is and why is it >>> necessary for those extensions. For a5xx+ it looks like some kind of an >>> internal address (what kind of?). For a4xx I'm completely lost. >> Yes, my bad. On at least a6xx+, shader could read 64b ALWAYSON counter >> from UCHE_TRAP_BASE+0 address. We use it to implement VK_KHR_shader_clock: >> "This extension advertises the SPIR-V ShaderClockKHR capability for Vulkan, >> which >> allows a shader to query a real-time or monotonically incrementing counter >> at >> the subgroup level or across the device level." >> And there is no other proper way to get such counter. Same with >> GL_ARB_shader_clock. > Yes, please add this to the commit message. Ok. >> Not sure what's there on older gens, I exposed the value on them for the >> completeness sake. But I don't know whether it is desired or not (I don't >> expect >> the value being read and used on a4xx/a5xx in Mesa). > Do you know if there is anything interesting in that region on a4xx / > a5xx (or at least if it's a region on a4xx?) Also how will that > GET_PARAM behave on a2xx-a3xx? Will it return 0 or some -EINVAL? I don't know if there is anything interesting there on a5xx or a4xx. I booted a5xx board I dug up, but found out that on a5xx we are even missing the instruction to read from memory address, so I wasn't able to check what's at that address. As for what to return on a2xx-a3xx, as suggested by Rob, I'll rebase on https://patchwork.freedesktop.org/series/141667/ then I will return EINVAL: if (adreno_gpu->uche_trap_base == 0) return UERR(EINVAL, drm, "no uche trap base"); >>>> Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com> >>>> --- >>>> drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 6 ++++-- >>>> drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 10 ++++++---- >>>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +++++++----- >>>> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 +++ >>>> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 ++ >>>> include/uapi/drm/msm_drm.h | 1 + >>>> 6 files changed, 23 insertions(+), 11 deletions(-) >>>> >>>> diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c >>>> index 50c490b492f0..f1b18a6663f7 100644 >>>> --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c >>>> +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c >>>> @@ -251,8 +251,8 @@ static int a4xx_hw_init(struct msm_gpu *gpu) >>>> gpu_write(gpu, REG_A4XX_UCHE_CACHE_WAYS_VFD, 0x07); >>>> /* Disable L2 bypass to avoid UCHE out of bounds errors */ >>>> - gpu_write(gpu, REG_A4XX_UCHE_TRAP_BASE_LO, 0xffff0000); >>>> - gpu_write(gpu, REG_A4XX_UCHE_TRAP_BASE_HI, 0xffff0000); >>>> + gpu_write(gpu, REG_A4XX_UCHE_TRAP_BASE_LO, lower_32_bits(adreno_gpu->uche_trap_base)); >>>> + gpu_write(gpu, REG_A4XX_UCHE_TRAP_BASE_HI, upper_32_bits(adreno_gpu->uche_trap_base)); >>>> gpu_write(gpu, REG_A4XX_CP_DEBUG, (1 << 25) | >>>> (adreno_is_a420(adreno_gpu) ? (1 << 29) : 0)); >>>> @@ -693,6 +693,8 @@ struct msm_gpu *a4xx_gpu_init(struct drm_device *dev) >>>> if (ret) >>>> goto fail; >>>> + adreno_gpu->uche_trap_base = 0xffff0000ffff0000ull; >>>> + >>>> if (!gpu->aspace) { >>>> /* TODO we think it is possible to configure the GPU to >>>> * restrict access to VRAM carveout. But the required >>>> diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c >>>> index ee89db72e36e..caf2c0a7a29f 100644 >>>> --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c >>>> +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c >>>> @@ -750,10 +750,10 @@ static int a5xx_hw_init(struct msm_gpu *gpu) >>>> gpu_write(gpu, REG_A5XX_UCHE_CACHE_WAYS, 0x02); >>>> /* Disable L2 bypass in the UCHE */ >>>> - gpu_write(gpu, REG_A5XX_UCHE_TRAP_BASE_LO, 0xFFFF0000); >>>> - gpu_write(gpu, REG_A5XX_UCHE_TRAP_BASE_HI, 0x0001FFFF); >>>> - gpu_write(gpu, REG_A5XX_UCHE_WRITE_THRU_BASE_LO, 0xFFFF0000); >>>> - gpu_write(gpu, REG_A5XX_UCHE_WRITE_THRU_BASE_HI, 0x0001FFFF); >>>> + gpu_write(gpu, REG_A5XX_UCHE_TRAP_BASE_LO, lower_32_bits(adreno_gpu->uche_trap_base)); >>>> + gpu_write(gpu, REG_A5XX_UCHE_TRAP_BASE_HI, upper_32_bits(adreno_gpu->uche_trap_base)); >>>> + gpu_write(gpu, REG_A5XX_UCHE_WRITE_THRU_BASE_LO, lower_32_bits(adreno_gpu->uche_trap_base)); >>>> + gpu_write(gpu, REG_A5XX_UCHE_WRITE_THRU_BASE_HI, upper_32_bits(adreno_gpu->uche_trap_base)); >>>> /* Set the GMEM VA range (0 to gpu->gmem) */ >>>> gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_LO, 0x00100000); >>>> @@ -1805,5 +1805,7 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) >>>> adreno_gpu->ubwc_config.macrotile_mode = 0; >>>> adreno_gpu->ubwc_config.ubwc_swizzle = 0x7; >>>> + adreno_gpu->uche_trap_base = 0x0001ffffffff0000ull; >>>> + >>>> return gpu; >>>> } >>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >>>> index 019610341df1..0ae29a7c8a4d 100644 >>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >>>> @@ -1123,12 +1123,12 @@ static int hw_init(struct msm_gpu *gpu) >>>> /* Disable L2 bypass in the UCHE */ >>>> if (adreno_is_a7xx(adreno_gpu)) { >>>> - gpu_write64(gpu, REG_A6XX_UCHE_TRAP_BASE, 0x0001fffffffff000llu); >>>> - gpu_write64(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE, 0x0001fffffffff000llu); >>>> + gpu_write64(gpu, REG_A6XX_UCHE_TRAP_BASE, adreno_gpu->uche_trap_base); >>>> + gpu_write64(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE, adreno_gpu->uche_trap_base); >>>> } else { >>>> - gpu_write64(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX, 0x0001ffffffffffc0llu); >>>> - gpu_write64(gpu, REG_A6XX_UCHE_TRAP_BASE, 0x0001fffffffff000llu); >>>> - gpu_write64(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE, 0x0001fffffffff000llu); >>>> + gpu_write64(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX, adreno_gpu->uche_trap_base + 0xfc0); >>>> + gpu_write64(gpu, REG_A6XX_UCHE_TRAP_BASE, adreno_gpu->uche_trap_base); >>>> + gpu_write64(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE, adreno_gpu->uche_trap_base); >>>> } >>>> if (!(adreno_is_a650_family(adreno_gpu) || >>>> @@ -2533,6 +2533,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) >>>> } >>>> } >>>> + adreno_gpu->uche_trap_base = 0x1fffffffff000ull; >>>> + >>>> if (gpu->aspace) >>>> msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu, >>>> a6xx_fault_handler); >>>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c >>>> index 076be0473eb5..774ff6eacb9f 100644 >>>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c >>>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c >>>> @@ -385,6 +385,9 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, >>>> case MSM_PARAM_MACROTILE_MODE: >>>> *value = adreno_gpu->ubwc_config.macrotile_mode; >>>> return 0; >>>> + case MSM_PARAM_UCHE_TRAP_BASE: >>>> + *value = adreno_gpu->uche_trap_base; >>>> + return 0; >>>> default: >>>> DBG("%s: invalid param: %u", gpu->name, param); >>>> return -EINVAL; >>>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h >>>> index e71f420f8b3a..9bd38dda4308 100644 >>>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h >>>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h >>>> @@ -253,6 +253,8 @@ struct adreno_gpu { >>>> bool gmu_is_wrapper; >>>> bool has_ray_tracing; >>>> + >>>> + u64 uche_trap_base; >>>> }; >>>> #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base) >>>> diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h >>>> index b916aab80dde..2342cb90857e 100644 >>>> --- a/include/uapi/drm/msm_drm.h >>>> +++ b/include/uapi/drm/msm_drm.h >>>> @@ -90,6 +90,7 @@ struct drm_msm_timespec { >>>> #define MSM_PARAM_RAYTRACING 0x11 /* RO */ >>>> #define MSM_PARAM_UBWC_SWIZZLE 0x12 /* RO */ >>>> #define MSM_PARAM_MACROTILE_MODE 0x13 /* RO */ >>>> +#define MSM_PARAM_UCHE_TRAP_BASE 0x14 /* RO */ >>>> /* For backwards compat. The original support for preemption was based on >>>> * a single ring per priority level so # of priority levels equals the # >>>> -- >>>> 2.46.2 >>>>
Depends on https://patchwork.freedesktop.org/series/141667/ The parameter would be used in [1] to implement VK_KHR_shader_clock and GL_ARB_shader_clock. On at least a6xx+, shader could read 64b ALWAYSON counter from UCHE_TRAP_BASE+0 address. Downstream driver exposes uche trap base via uapi only on A7XX+. However, from testing, we could get correct shader clock on A6XX. The uche trap base value is not used by Mesa for A4XX and A5XX. [1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29860 Danylo Piliaiev (1): drm/msm: Expose uche trap base via uapi drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 6 ++++-- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 10 ++++++---- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +++++++----- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 5 +++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 ++ include/uapi/drm/msm_drm.h | 1 + 6 files changed, 25 insertions(+), 11 deletions(-)