| Message ID | 20241203190236.505759-1-maz@kernel.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | KVM: arm64: Do not allow ID_AA64MMFR0_EL1.ASIDbits to be overridden | expand |
On Tue, Dec 03, 2024 at 07:02:36PM +0000, Marc Zyngier wrote: > Catalin reports that a hypervisor lying to a guest about the size > of the ASID field may result in unexpected issues: > > - if the underlying HW does only supports 8 bit ASIDs, the ASID > field in a TLBI VAE1* operation is only 8 bits, and the HW will > ignore the other 8 bits > > - if on the contrary the HW is 16 bit capable, the ASID field > in the same TLBI operation is always 16 bits, irrespective of > the value of TCR_ELx.AS. > > This could lead to missed invalidations if the guest was lead to > assume that the HW had 8 bit ASIDs while they really are 16 bit wide. > > In order to avoid any potential disaster that would be hard to debug, > prenent the migration between a host with 8 bit ASIDs to one with > wider ASIDs (the converse was obviously always forbidden). This is > also consistent with what we already do for VMIDs. > > If it becomes absolutely mandatory to support such a migration path > in the future, we will have to trap and emulate all TLBIs, something > that nobody should look forward to. > > Fixes: d5a32b60dc18 ("KVM: arm64: Allow userspace to change ID_AA64MMFR{0-2}_EL1") > Reported-by: Catalin Marinas <catalin.marinas@arm.com> > Signed-off-by: Marc Zyngier <maz@kernel.org> > Cc: stable@vger.kernel.org > Cc: Will Deacon <will@kernel.org> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: Marc Zyngier <maz@kernel.org> > Cc: James Morse <james.morse@arm.com> > Cc: Oliver Upton <oliver.upton@linux.dev> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
On Tue, 03 Dec 2024 19:02:36 +0000, Marc Zyngier wrote: > Catalin reports that a hypervisor lying to a guest about the size > of the ASID field may result in unexpected issues: > > - if the underlying HW does only supports 8 bit ASIDs, the ASID > field in a TLBI VAE1* operation is only 8 bits, and the HW will > ignore the other 8 bits > > [...] Applied to fixes, thanks! [1/1] KVM: arm64: Do not allow ID_AA64MMFR0_EL1.ASIDbits to be overridden https://git.kernel.org/kvmarm/kvmarm/c/03c7527e97f7 -- Best, Oliver
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index a26f02ec8748..b1918adbd0aa 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2674,7 +2674,8 @@ static const struct sys_reg_desc sys_reg_descs[] = { ID_WRITABLE(ID_AA64MMFR0_EL1, ~(ID_AA64MMFR0_EL1_RES0 | ID_AA64MMFR0_EL1_TGRAN4_2 | ID_AA64MMFR0_EL1_TGRAN64_2 | - ID_AA64MMFR0_EL1_TGRAN16_2)), + ID_AA64MMFR0_EL1_TGRAN16_2 | + ID_AA64MMFR0_EL1_ASIDBITS)), ID_WRITABLE(ID_AA64MMFR1_EL1, ~(ID_AA64MMFR1_EL1_RES0 | ID_AA64MMFR1_EL1_HCX | ID_AA64MMFR1_EL1_TWED |
Catalin reports that a hypervisor lying to a guest about the size of the ASID field may result in unexpected issues: - if the underlying HW does only supports 8 bit ASIDs, the ASID field in a TLBI VAE1* operation is only 8 bits, and the HW will ignore the other 8 bits - if on the contrary the HW is 16 bit capable, the ASID field in the same TLBI operation is always 16 bits, irrespective of the value of TCR_ELx.AS. This could lead to missed invalidations if the guest was lead to assume that the HW had 8 bit ASIDs while they really are 16 bit wide. In order to avoid any potential disaster that would be hard to debug, prenent the migration between a host with 8 bit ASIDs to one with wider ASIDs (the converse was obviously always forbidden). This is also consistent with what we already do for VMIDs. If it becomes absolutely mandatory to support such a migration path in the future, we will have to trap and emulate all TLBIs, something that nobody should look forward to. Fixes: d5a32b60dc18 ("KVM: arm64: Allow userspace to change ID_AA64MMFR{0-2}_EL1") Reported-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Cc: stable@vger.kernel.org Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Marc Zyngier <maz@kernel.org> Cc: James Morse <james.morse@arm.com> Cc: Oliver Upton <oliver.upton@linux.dev> --- arch/arm64/kvm/sys_regs.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)