| Message ID | 20241203165450.1501219-3-heiko@sntech.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/rockchip: Add driver for the new DSI2 controller | expand |
Hi Heiko, On 12/4/24 00:54, Heiko Stuebner wrote: > From: Heiko Stuebner <heiko.stuebner@cherry.de> > > The Display Serial Interface 2 (DSI-2) is part of a group of communication > protocols defined by the MIPI Alliance. The RK3588 implements this > specification in its two MIPI DSI-2 Host Controllers that are based on a > new Synopsis IP. Synopsys ? > > Reviewed-by: Rob Herring (Arm) <robh@kernel.org> > Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de> > --- > .../rockchip/rockchip,rk3588-mipi-dsi2.yaml | 119 ++++++++++++++++++ > 1 file changed, 119 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml > > diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml > new file mode 100644 > index 000000000000..7c017e927223 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml > @@ -0,0 +1,119 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Rockchip specific extensions to the Synopsys Designware MIPI DSI2 > + > +maintainers: > + - Heiko Stuebner <heiko@sntech.de> > + > +properties: > + compatible: > + enum: > + - rockchip,rk3588-mipi-dsi2 > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + maxItems: 2 > + > + clock-names: > + items: > + - const: pclk > + - const: sys > + > + rockchip,grf: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + This SoC uses GRF regs to switch between vopl/vopb. > + > + phys: > + maxItems: 1 > + > + phy-names: > + const: dcphy > + > + power-domains: > + maxItems: 1 > + > + resets: > + maxItems: 1 > + > + reset-names: > + const: apb > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/properties/port > + description: Input node to receive pixel data. > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: DSI output node to panel. > + > + required: > + - port@0 > + - port@1 > + > +required: > + - compatible > + - clocks > + - clock-names > + - rockchip,grf > + - phys > + - phy-names > + - ports > + - reg > + > +allOf: > + - $ref: /schemas/display/dsi-controller.yaml# > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/rockchip,rk3588-cru.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + #include <dt-bindings/power/rk3588-power.h> > + #include <dt-bindings/reset/rockchip,rk3588-cru.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + dsi@fde20000 { > + compatible = "rockchip,rk3588-mipi-dsi2"; > + reg = <0x0 0xfde20000 0x0 0x10000>; > + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>; > + clock-names = "pclk", "sys"; > + resets = <&cru SRST_P_DSIHOST0>; > + reset-names = "apb"; > + power-domains = <&power RK3588_PD_VOP>; > + phys = <&mipidcphy0>; > + phy-names = "dcphy"; > + rockchip,grf = <&vop_grf>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + dsi0_in: port@0 { > + reg = <0>; > + }; > + > + dsi0_out: port@1 { > + reg = <1>; > + }; > + }; > + }; > + };
Hi Heiko, On 12/4/24 00:54, Heiko Stuebner wrote: > From: Heiko Stuebner <heiko.stuebner@cherry.de> > > The Display Serial Interface 2 (DSI-2) is part of a group of communication > protocols defined by the MIPI Alliance. The RK3588 implements this > specification in its two MIPI DSI-2 Host Controllers that are based on a > new Synopsis IP. > > Reviewed-by: Rob Herring (Arm) <robh@kernel.org> > Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de> > --- > .../rockchip/rockchip,rk3588-mipi-dsi2.yaml | 119 ++++++++++++++++++ > 1 file changed, 119 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml > > diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml > new file mode 100644 > index 000000000000..7c017e927223 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml > @@ -0,0 +1,119 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Rockchip specific extensions to the Synopsys Designware MIPI DSI2 > + > +maintainers: > + - Heiko Stuebner <heiko@sntech.de> > + > +properties: > + compatible: > + enum: > + - rockchip,rk3588-mipi-dsi2 > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + maxItems: 2 > + > + clock-names: > + items: > + - const: pclk > + - const: sys > + > + rockchip,grf: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + This SoC uses GRF regs to switch between vopl/vopb. > + > + phys: > + maxItems: 1 > + > + phy-names: > + const: dcphy > + > + power-domains: > + maxItems: 1 > + > + resets: > + maxItems: 1 > + > + reset-names: > + const: apb > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/properties/port > + description: Input node to receive pixel data. > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: DSI output node to panel. > + > + required: > + - port@0 > + - port@1 > + > +required: > + - compatible > + - clocks > + - clock-names > + - rockchip,grf > + - phys > + - phy-names > + - ports > + - reg > + > +allOf: > + - $ref: /schemas/display/dsi-controller.yaml# > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/rockchip,rk3588-cru.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + #include <dt-bindings/power/rk3588-power.h> > + #include <dt-bindings/reset/rockchip,rk3588-cru.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + dsi@fde20000 { > + compatible = "rockchip,rk3588-mipi-dsi2"; > + reg = <0x0 0xfde20000 0x0 0x10000>; > + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>; > + clock-names = "pclk", "sys"; > + resets = <&cru SRST_P_DSIHOST0>; > + reset-names = "apb"; > + power-domains = <&power RK3588_PD_VOP>; > + phys = <&mipidcphy0>; Should it be phys = <&mipidcphy0 PHY_TYPE_DPHY>, as the #phy-cells = 1 on phy side ? > + phy-names = "dcphy"; > + rockchip,grf = <&vop_grf>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + dsi0_in: port@0 { > + reg = <0>; > + }; > + > + dsi0_out: port@1 { > + reg = <1>; > + }; > + }; > + }; > + };
diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml new file mode 100644 index 000000000000..7c017e927223 --- /dev/null +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml @@ -0,0 +1,119 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip specific extensions to the Synopsys Designware MIPI DSI2 + +maintainers: + - Heiko Stuebner <heiko@sntech.de> + +properties: + compatible: + enum: + - rockchip,rk3588-mipi-dsi2 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: pclk + - const: sys + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + This SoC uses GRF regs to switch between vopl/vopb. + + phys: + maxItems: 1 + + phy-names: + const: dcphy + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + reset-names: + const: apb + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Input node to receive pixel data. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: DSI output node to panel. + + required: + - port@0 + - port@1 + +required: + - compatible + - clocks + - clock-names + - rockchip,grf + - phys + - phy-names + - ports + - reg + +allOf: + - $ref: /schemas/display/dsi-controller.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/rockchip,rk3588-cru.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/power/rk3588-power.h> + #include <dt-bindings/reset/rockchip,rk3588-cru.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + dsi@fde20000 { + compatible = "rockchip,rk3588-mipi-dsi2"; + reg = <0x0 0xfde20000 0x0 0x10000>; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>; + clock-names = "pclk", "sys"; + resets = <&cru SRST_P_DSIHOST0>; + reset-names = "apb"; + power-domains = <&power RK3588_PD_VOP>; + phys = <&mipidcphy0>; + phy-names = "dcphy"; + rockchip,grf = <&vop_grf>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + dsi0_in: port@0 { + reg = <0>; + }; + + dsi0_out: port@1 { + reg = <1>; + }; + }; + }; + };