Message ID | 20241203-gs101-phy-lanes-orientation-phy-v2-1-40dcf1b7670d@linaro.org (mailing list archive) |
---|---|
State | New |
Headers | show |
Series | USB31DRD phy updates for Google Tensor gs101 (orientation & DWC3 rpm) | expand |
On Tue, Dec 03, 2024 at 12:13:49PM +0000, André Draszik wrote: > In [1], Rob pointed out that we should really be separating properties > with blank lines in between, which is universal style. Only where > properties are booleans, empty lines are not required. In the subject, just say 'add blank lines between DT properties'. 'universal style' could be anything. > > Do so. > > Link: https://lore.kernel.org/all/20240711212359.GA3023490-robh@kernel.org/ [1] > Reviewed-by: Peter Griffin <peter.griffin@linaro.org> > Signed-off-by: André Draszik <andre.draszik@linaro.org> > > --- > v2: > * collect tags > --- > .../devicetree/bindings/phy/samsung,usb3-drd-phy.yaml | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) Acked-by: Rob Herring (Arm) <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml index 16321cdd4919..1f8b35917b11 100644 --- a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml @@ -83,14 +83,19 @@ properties: pll-supply: description: Power supply for the USB PLL. + dvdd-usb20-supply: description: DVDD power supply for the USB 2.0 phy. + vddh-usb20-supply: description: VDDh power supply for the USB 2.0 phy. + vdd33-usb20-supply: description: 3.3V power supply for the USB 2.0 phy. + vdda-usbdp-supply: description: VDDa power supply for the USB DP phy. + vddh-usbdp-supply: description: VDDh power supply for the USB DP phy. @@ -117,6 +122,7 @@ allOf: - description: Gate of control interface AXI clock - description: Gate of control interface APB clock - description: Gate of SCL APB clock + clock-names: items: - const: phy @@ -124,10 +130,13 @@ allOf: - const: ctrl_aclk - const: ctrl_pclk - const: scl_pclk + reg: minItems: 3 + reg-names: minItems: 3 + required: - reg-names - pll-supply @@ -149,6 +158,7 @@ allOf: clocks: minItems: 5 maxItems: 5 + clock-names: items: - const: phy @@ -156,8 +166,10 @@ allOf: - const: phy_utmi - const: phy_pipe - const: itp + reg: maxItems: 1 + reg-names: maxItems: 1 @@ -174,12 +186,15 @@ allOf: clocks: minItems: 2 maxItems: 2 + clock-names: items: - const: phy - const: ref + reg: maxItems: 1 + reg-names: maxItems: 1