| Message ID | 20241206111337.726244-14-claudiu.beznea.uj@bp.renesas.com (mailing list archive) |
|---|---|
| State | New |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | iio: adc: rzg2l_adc: Add support for RZ/G3S | expand |
On Fri, 6 Dec 2024 13:13:35 +0200 Claudiu <claudiu.beznea@tuxon.dev> wrote: > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > Add ADC support for the Renesas RZ/G3S SoC. The key features of this IP > include: > - 9 channels, with one dedicated to reading the temperature reported by the > Thermal Sensor Unit (TSU) > - A different default ADCMP value, which is written to the ADM3 register. > - Different default sampling rates > - ADM3.ADSMP field is 8 bits wide > - ADINT.INTEN field is 11 bits wide > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Hi Claudiu As my comments were all minor stuff, I have applied this. However they were the sort of minor changes that result in lots of fuzz and hand editing when applying so please check the result. Applied to the testing branch of iio.git. Thanks, Jonathan > --- > > Changes in v2: > - none > > drivers/iio/adc/rzg2l_adc.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/drivers/iio/adc/rzg2l_adc.c b/drivers/iio/adc/rzg2l_adc.c > index 2a911269a358..81904e2c4075 100644 > --- a/drivers/iio/adc/rzg2l_adc.c > +++ b/drivers/iio/adc/rzg2l_adc.c > @@ -502,7 +502,16 @@ static const struct rzg2l_adc_hw_params rzg2l_hw_params = { > .adivc = true > }; > > +static const struct rzg2l_adc_hw_params rzg3s_hw_params = { > + .num_channels = 9, > + .default_adcmp = 0x1d, > + .default_adsmp = { 0x7f, 0xff }, > + .adsmp_mask = GENMASK(7, 0), > + .adint_inten_mask = GENMASK(11, 0), > +}; > + > static const struct of_device_id rzg2l_adc_match[] = { > + { .compatible = "renesas,r9a08g045-adc", .data = &rzg3s_hw_params }, > { .compatible = "renesas,rzg2l-adc", .data = &rzg2l_hw_params }, > { /* sentinel */ } > };
Hi, Jonathan, On 07.12.2024 20:34, Jonathan Cameron wrote: > On Fri, 6 Dec 2024 13:13:35 +0200 > Claudiu <claudiu.beznea@tuxon.dev> wrote: > >> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> >> >> Add ADC support for the Renesas RZ/G3S SoC. The key features of this IP >> include: >> - 9 channels, with one dedicated to reading the temperature reported by the >> Thermal Sensor Unit (TSU) >> - A different default ADCMP value, which is written to the ADM3 register. >> - Different default sampling rates >> - ADM3.ADSMP field is 8 bits wide >> - ADINT.INTEN field is 11 bits wide >> >> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > Hi Claudiu > > As my comments were all minor stuff, I have applied this. > However they were the sort of minor changes that result in lots of > fuzz and hand editing when applying so please check the result. > Applied to the testing branch of iio.git. I checked and tested testing branch at iio.git. Everything is good. Thank you for taking care of this, Claudiu > > Thanks, > > Jonathan
diff --git a/drivers/iio/adc/rzg2l_adc.c b/drivers/iio/adc/rzg2l_adc.c index 2a911269a358..81904e2c4075 100644 --- a/drivers/iio/adc/rzg2l_adc.c +++ b/drivers/iio/adc/rzg2l_adc.c @@ -502,7 +502,16 @@ static const struct rzg2l_adc_hw_params rzg2l_hw_params = { .adivc = true }; +static const struct rzg2l_adc_hw_params rzg3s_hw_params = { + .num_channels = 9, + .default_adcmp = 0x1d, + .default_adsmp = { 0x7f, 0xff }, + .adsmp_mask = GENMASK(7, 0), + .adint_inten_mask = GENMASK(11, 0), +}; + static const struct of_device_id rzg2l_adc_match[] = { + { .compatible = "renesas,r9a08g045-adc", .data = &rzg3s_hw_params }, { .compatible = "renesas,rzg2l-adc", .data = &rzg2l_hw_params }, { /* sentinel */ } };