| Message ID | 20241206-rcar-gh-dsi-v3-5-d74c2166fa15@ideasonboard.com (mailing list archive) |
|---|---|
| State | Under Review |
| Headers | show |
| Series | drm: Add DSI/DP support for Renesas r8a779h0 V4M and grey-hawk board | expand |
Hi Tomi, On Fri, Dec 6, 2024 at 10:33 AM Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> wrote: > From: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> > > Add display related clocks for DU, DSI, FCPVD, and VSPD. > > Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> > Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> > Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-clk for v6.14. > --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c > +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c > @@ -179,6 +179,9 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = { > DEF_MOD("canfd0", 328, R8A779H0_CLK_SASYNCPERD2), > DEF_MOD("csi40", 331, R8A779H0_CLK_CSI), > DEF_MOD("csi41", 400, R8A779H0_CLK_CSI), > + DEF_MOD("dis0", 411, R8A779H0_CLK_S0D3), > + DEF_MOD("dsitxlink0", 415, R8A779H0_CLK_DSIREF), > + DEF_MOD("fcpvd0", 508, R8A779H0_CLK_S0D3), > DEF_MOD("hscif0", 514, R8A779H0_CLK_SASYNCPERD1), > DEF_MOD("hscif1", 515, R8A779H0_CLK_SASYNCPERD1), > DEF_MOD("hscif2", 516, R8A779H0_CLK_SASYNCPERD1), > @@ -227,6 +230,7 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = { > DEF_MOD("vin15", 811, R8A779H0_CLK_S0D4_VIO), > DEF_MOD("vin16", 812, R8A779H0_CLK_S0D4_VIO), > DEF_MOD("vin17", 813, R8A779H0_CLK_S0D4_VIO), > + DEF_MOD("vspd0", 830, R8A779H0_CLK_S0D1_VIO), > DEF_MOD("wdt1:wdt0", 907, R8A779H0_CLK_R), > DEF_MOD("cmt0", 910, R8A779H0_CLK_R), > DEF_MOD("cmt1", 911, R8A779H0_CLK_R), As mentioned by Laurent during his review on v1, all clock parents should probably be some form of R8A779H0_CLK_S0Dx_VIO. So I'm inclined to replace all of them by R8A779H0_CLK_VIOBUSD2 while applying, which would match R-Car V4H. Are you OK with that? Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi, On 06/12/2024 15:43, Geert Uytterhoeven wrote: > Hi Tomi, > > On Fri, Dec 6, 2024 at 10:33 AM Tomi Valkeinen > <tomi.valkeinen@ideasonboard.com> wrote: >> From: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> >> >> Add display related clocks for DU, DSI, FCPVD, and VSPD. >> >> Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> >> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> >> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > i.e. will queue in renesas-clk for v6.14. > >> --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c >> +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c >> @@ -179,6 +179,9 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = { >> DEF_MOD("canfd0", 328, R8A779H0_CLK_SASYNCPERD2), >> DEF_MOD("csi40", 331, R8A779H0_CLK_CSI), >> DEF_MOD("csi41", 400, R8A779H0_CLK_CSI), >> + DEF_MOD("dis0", 411, R8A779H0_CLK_S0D3), >> + DEF_MOD("dsitxlink0", 415, R8A779H0_CLK_DSIREF), >> + DEF_MOD("fcpvd0", 508, R8A779H0_CLK_S0D3), >> DEF_MOD("hscif0", 514, R8A779H0_CLK_SASYNCPERD1), >> DEF_MOD("hscif1", 515, R8A779H0_CLK_SASYNCPERD1), >> DEF_MOD("hscif2", 516, R8A779H0_CLK_SASYNCPERD1), >> @@ -227,6 +230,7 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = { >> DEF_MOD("vin15", 811, R8A779H0_CLK_S0D4_VIO), >> DEF_MOD("vin16", 812, R8A779H0_CLK_S0D4_VIO), >> DEF_MOD("vin17", 813, R8A779H0_CLK_S0D4_VIO), >> + DEF_MOD("vspd0", 830, R8A779H0_CLK_S0D1_VIO), >> DEF_MOD("wdt1:wdt0", 907, R8A779H0_CLK_R), >> DEF_MOD("cmt0", 910, R8A779H0_CLK_R), >> DEF_MOD("cmt1", 911, R8A779H0_CLK_R), > > As mentioned by Laurent during his review on v1, all clock parents > should probably be some form of R8A779H0_CLK_S0Dx_VIO. > So I'm inclined to replace all of them by R8A779H0_CLK_VIOBUSD2 while > applying, which would match R-Car V4H. What do you mean with the above? First you say the clock parents should be some form of S0Dx_VIO, but then you say you'll use VIOBUSD2. Aren't those unrelated clocks, from different PLLs? > Are you OK with that? I'm fine with that. I can't really get much out of the docs wrt. clocking, and the clocks I used were from the BSP. Afaics, it looks similar to V4H, so it's probably best have the same clocks, as you suggest. Tomi
Hi Tomi, On Mon, Dec 9, 2024 at 6:26 AM Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> wrote: > On 06/12/2024 15:43, Geert Uytterhoeven wrote: > > On Fri, Dec 6, 2024 at 10:33 AM Tomi Valkeinen > > <tomi.valkeinen@ideasonboard.com> wrote: > >> From: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> > >> > >> Add display related clocks for DU, DSI, FCPVD, and VSPD. > >> > >> Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> > >> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> > >> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> > > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > i.e. will queue in renesas-clk for v6.14. > > > >> --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c > >> +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c > >> @@ -179,6 +179,9 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = { > >> DEF_MOD("canfd0", 328, R8A779H0_CLK_SASYNCPERD2), > >> DEF_MOD("csi40", 331, R8A779H0_CLK_CSI), > >> DEF_MOD("csi41", 400, R8A779H0_CLK_CSI), > >> + DEF_MOD("dis0", 411, R8A779H0_CLK_S0D3), > >> + DEF_MOD("dsitxlink0", 415, R8A779H0_CLK_DSIREF), > >> + DEF_MOD("fcpvd0", 508, R8A779H0_CLK_S0D3), > >> DEF_MOD("hscif0", 514, R8A779H0_CLK_SASYNCPERD1), > >> DEF_MOD("hscif1", 515, R8A779H0_CLK_SASYNCPERD1), > >> DEF_MOD("hscif2", 516, R8A779H0_CLK_SASYNCPERD1), > >> @@ -227,6 +230,7 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = { > >> DEF_MOD("vin15", 811, R8A779H0_CLK_S0D4_VIO), > >> DEF_MOD("vin16", 812, R8A779H0_CLK_S0D4_VIO), > >> DEF_MOD("vin17", 813, R8A779H0_CLK_S0D4_VIO), > >> + DEF_MOD("vspd0", 830, R8A779H0_CLK_S0D1_VIO), > >> DEF_MOD("wdt1:wdt0", 907, R8A779H0_CLK_R), > >> DEF_MOD("cmt0", 910, R8A779H0_CLK_R), > >> DEF_MOD("cmt1", 911, R8A779H0_CLK_R), > > > > As mentioned by Laurent during his review on v1, all clock parents > > should probably be some form of R8A779H0_CLK_S0Dx_VIO. > > So I'm inclined to replace all of them by R8A779H0_CLK_VIOBUSD2 while > > applying, which would match R-Car V4H. > > What do you mean with the above? First you say the clock parents should > be some form of S0Dx_VIO, but then you say you'll use VIOBUSD2. Aren't > those unrelated clocks, from different PLLs? Oops, copy-'n-paste went wrong. I did mean R8A779H0_VIOBUSD*. > > Are you OK with that? > > I'm fine with that. I can't really get much out of the docs wrt. > clocking, and the clocks I used were from the BSP. Afaics, it looks > similar to V4H, so it's probably best have the same clocks, as you suggest. Agreed. Gr{oetje,eeting}s, Geert
On Mon, Dec 09, 2024 at 08:49:18AM +0100, Geert Uytterhoeven wrote: > On Mon, Dec 9, 2024 at 6:26 AM Tomi Valkeinen wrote: > > On 06/12/2024 15:43, Geert Uytterhoeven wrote: > > > On Fri, Dec 6, 2024 at 10:33 AM Tomi Valkeinen wrote: > > >> From: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> > > >> > > >> Add display related clocks for DU, DSI, FCPVD, and VSPD. > > >> > > >> Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> > > >> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> > > >> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> > > > > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > > i.e. will queue in renesas-clk for v6.14. > > > > > >> --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c > > >> +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c > > >> @@ -179,6 +179,9 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = { > > >> DEF_MOD("canfd0", 328, R8A779H0_CLK_SASYNCPERD2), > > >> DEF_MOD("csi40", 331, R8A779H0_CLK_CSI), > > >> DEF_MOD("csi41", 400, R8A779H0_CLK_CSI), > > >> + DEF_MOD("dis0", 411, R8A779H0_CLK_S0D3), > > >> + DEF_MOD("dsitxlink0", 415, R8A779H0_CLK_DSIREF), > > >> + DEF_MOD("fcpvd0", 508, R8A779H0_CLK_S0D3), > > >> DEF_MOD("hscif0", 514, R8A779H0_CLK_SASYNCPERD1), > > >> DEF_MOD("hscif1", 515, R8A779H0_CLK_SASYNCPERD1), > > >> DEF_MOD("hscif2", 516, R8A779H0_CLK_SASYNCPERD1), > > >> @@ -227,6 +230,7 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = { > > >> DEF_MOD("vin15", 811, R8A779H0_CLK_S0D4_VIO), > > >> DEF_MOD("vin16", 812, R8A779H0_CLK_S0D4_VIO), > > >> DEF_MOD("vin17", 813, R8A779H0_CLK_S0D4_VIO), > > >> + DEF_MOD("vspd0", 830, R8A779H0_CLK_S0D1_VIO), > > >> DEF_MOD("wdt1:wdt0", 907, R8A779H0_CLK_R), > > >> DEF_MOD("cmt0", 910, R8A779H0_CLK_R), > > >> DEF_MOD("cmt1", 911, R8A779H0_CLK_R), > > > > > > As mentioned by Laurent during his review on v1, all clock parents > > > should probably be some form of R8A779H0_CLK_S0Dx_VIO. > > > So I'm inclined to replace all of them by R8A779H0_CLK_VIOBUSD2 while > > > applying, which would match R-Car V4H. > > > > What do you mean with the above? First you say the clock parents should > > be some form of S0Dx_VIO, but then you say you'll use VIOBUSD2. Aren't > > those unrelated clocks, from different PLLs? > > Oops, copy-'n-paste went wrong. I did mean R8A779H0_VIOBUSD*. > > > > Are you OK with that? > > > > I'm fine with that. I can't really get much out of the docs wrt. > > clocking, and the clocks I used were from the BSP. Afaics, it looks > > similar to V4H, so it's probably best have the same clocks, as you suggest. > > Agreed. Works for me too.
diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c index e20c048bfa9b..dc37e987c0e6 100644 --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c @@ -179,6 +179,9 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = { DEF_MOD("canfd0", 328, R8A779H0_CLK_SASYNCPERD2), DEF_MOD("csi40", 331, R8A779H0_CLK_CSI), DEF_MOD("csi41", 400, R8A779H0_CLK_CSI), + DEF_MOD("dis0", 411, R8A779H0_CLK_S0D3), + DEF_MOD("dsitxlink0", 415, R8A779H0_CLK_DSIREF), + DEF_MOD("fcpvd0", 508, R8A779H0_CLK_S0D3), DEF_MOD("hscif0", 514, R8A779H0_CLK_SASYNCPERD1), DEF_MOD("hscif1", 515, R8A779H0_CLK_SASYNCPERD1), DEF_MOD("hscif2", 516, R8A779H0_CLK_SASYNCPERD1), @@ -227,6 +230,7 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = { DEF_MOD("vin15", 811, R8A779H0_CLK_S0D4_VIO), DEF_MOD("vin16", 812, R8A779H0_CLK_S0D4_VIO), DEF_MOD("vin17", 813, R8A779H0_CLK_S0D4_VIO), + DEF_MOD("vspd0", 830, R8A779H0_CLK_S0D1_VIO), DEF_MOD("wdt1:wdt0", 907, R8A779H0_CLK_R), DEF_MOD("cmt0", 910, R8A779H0_CLK_R), DEF_MOD("cmt1", 911, R8A779H0_CLK_R),