| Message ID | 20241206-rcar-gh-dsi-v3-2-d74c2166fa15@ideasonboard.com (mailing list archive) |
|---|---|
| State | Under Review |
| Headers | show |
| Series | drm: Add DSI/DP support for Renesas r8a779h0 V4M and grey-hawk board | expand |
Hi Tomi, Thank you for the patch. On Fri, Dec 06, 2024 at 11:32:35AM +0200, Tomi Valkeinen wrote: > From: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> > > Currently the driver always writes DPTSR when setting up the hardware. > However, writing the register is only meaningful when the second source > for a plane is used, and the register is not even documented for SoCs > that do not have the second source. I've confirmed that for all the models currently supported by the DU driver. > So move the write behind a condition. > > Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> I will test the series on an M3N board. > --- > drivers/gpu/drm/renesas/rcar-du/rcar_du_group.c | 20 +++++++++++++++----- > 1 file changed, 15 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_du_group.c b/drivers/gpu/drm/renesas/rcar-du/rcar_du_group.c > index 2ccd2581f544..1ec806c8e013 100644 > --- a/drivers/gpu/drm/renesas/rcar-du/rcar_du_group.c > +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_du_group.c > @@ -185,11 +185,21 @@ static void rcar_du_group_setup(struct rcar_du_group *rgrp) > dorcr |= DORCR_PG1T | DORCR_DK1S | DORCR_PG1D_DS1; > rcar_du_group_write(rgrp, DORCR, dorcr); > > - /* Apply planes to CRTCs association. */ > - mutex_lock(&rgrp->lock); > - rcar_du_group_write(rgrp, DPTSR, (rgrp->dptsr_planes << 16) | > - rgrp->dptsr_planes); > - mutex_unlock(&rgrp->lock); > + /* > + * DPTSR is used to select the source for the planes of a group. The > + * first source is chosen by writing 0 to the respective bits, and this > + * is always the default value of the register. In other words, writing > + * DPTSR is only needed if the SoC supports choosing the second source. > + * > + * The SoCs documentations seems to confirm this, as the DPTSR register > + * is not documented if only the first source exists on that SoC. > + */ > + if (rgrp->channels_mask & BIT(1)) { > + mutex_lock(&rgrp->lock); > + rcar_du_group_write(rgrp, DPTSR, (rgrp->dptsr_planes << 16) | > + rgrp->dptsr_planes); > + mutex_unlock(&rgrp->lock); > + } > } > > /* >
On Tue, Dec 10, 2024 at 01:04:19AM +0200, Laurent Pinchart wrote: > On Fri, Dec 06, 2024 at 11:32:35AM +0200, Tomi Valkeinen wrote: > > From: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> > > > > Currently the driver always writes DPTSR when setting up the hardware. > > However, writing the register is only meaningful when the second source > > for a plane is used, and the register is not even documented for SoCs > > that do not have the second source. > > I've confirmed that for all the models currently supported by the DU > driver. > > > So move the write behind a condition. > > > > Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> > > Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> > > I will test the series on an M3N board. Tested-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> # On R-Car M3-N > > --- > > drivers/gpu/drm/renesas/rcar-du/rcar_du_group.c | 20 +++++++++++++++----- > > 1 file changed, 15 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_du_group.c b/drivers/gpu/drm/renesas/rcar-du/rcar_du_group.c > > index 2ccd2581f544..1ec806c8e013 100644 > > --- a/drivers/gpu/drm/renesas/rcar-du/rcar_du_group.c > > +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_du_group.c > > @@ -185,11 +185,21 @@ static void rcar_du_group_setup(struct rcar_du_group *rgrp) > > dorcr |= DORCR_PG1T | DORCR_DK1S | DORCR_PG1D_DS1; > > rcar_du_group_write(rgrp, DORCR, dorcr); > > > > - /* Apply planes to CRTCs association. */ > > - mutex_lock(&rgrp->lock); > > - rcar_du_group_write(rgrp, DPTSR, (rgrp->dptsr_planes << 16) | > > - rgrp->dptsr_planes); > > - mutex_unlock(&rgrp->lock); > > + /* > > + * DPTSR is used to select the source for the planes of a group. The > > + * first source is chosen by writing 0 to the respective bits, and this > > + * is always the default value of the register. In other words, writing > > + * DPTSR is only needed if the SoC supports choosing the second source. > > + * > > + * The SoCs documentations seems to confirm this, as the DPTSR register > > + * is not documented if only the first source exists on that SoC. > > + */ > > + if (rgrp->channels_mask & BIT(1)) { > > + mutex_lock(&rgrp->lock); > > + rcar_du_group_write(rgrp, DPTSR, (rgrp->dptsr_planes << 16) | > > + rgrp->dptsr_planes); > > + mutex_unlock(&rgrp->lock); > > + } > > } > > > > /* > >
diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_du_group.c b/drivers/gpu/drm/renesas/rcar-du/rcar_du_group.c index 2ccd2581f544..1ec806c8e013 100644 --- a/drivers/gpu/drm/renesas/rcar-du/rcar_du_group.c +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_du_group.c @@ -185,11 +185,21 @@ static void rcar_du_group_setup(struct rcar_du_group *rgrp) dorcr |= DORCR_PG1T | DORCR_DK1S | DORCR_PG1D_DS1; rcar_du_group_write(rgrp, DORCR, dorcr); - /* Apply planes to CRTCs association. */ - mutex_lock(&rgrp->lock); - rcar_du_group_write(rgrp, DPTSR, (rgrp->dptsr_planes << 16) | - rgrp->dptsr_planes); - mutex_unlock(&rgrp->lock); + /* + * DPTSR is used to select the source for the planes of a group. The + * first source is chosen by writing 0 to the respective bits, and this + * is always the default value of the register. In other words, writing + * DPTSR is only needed if the SoC supports choosing the second source. + * + * The SoCs documentations seems to confirm this, as the DPTSR register + * is not documented if only the first source exists on that SoC. + */ + if (rgrp->channels_mask & BIT(1)) { + mutex_lock(&rgrp->lock); + rcar_du_group_write(rgrp, DPTSR, (rgrp->dptsr_planes << 16) | + rgrp->dptsr_planes); + mutex_unlock(&rgrp->lock); + } } /*