| Message ID | 20241209134459.27110-4-ansuelsmth@gmail.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | net: dsa: Add Airoha AN8855 support | expand |
On Mon, Dec 09, 2024 at 02:44:20PM +0100, Christian Marangi wrote: > Document support for Airoha AN8855 5-port Gigabit Switch. > > It does expose the 5 Internal PHYs on the MDIO bus and each port > can access the Switch register space by configurting the PHY page. typo: configuring Also below. > > Each internal PHY might require calibration with the fused EFUSE on > the switch exposed by the Airoha AN8855 SoC NVMEM. This paragraph should be irrelevant to the switch binding. > > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> > --- > .../net/dsa/airoha,an8855-switch.yaml | 105 ++++++++++++++++++ > MAINTAINERS | 1 + > 2 files changed, 106 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml > > diff --git a/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml b/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml > new file mode 100644 > index 000000000000..63bcbebd6a29 > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml > @@ -0,0 +1,105 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/net/dsa/airoha,an8855-switch.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Airoha AN8855 Gigabit Switch > + > +maintainers: > + - Christian Marangi <ansuelsmth@gmail.com> > + > +description: > > + Airoha AN8855 is a 5-port Gigabit Switch. > + > + It does expose the 5 Internal PHYs on the MDIO bus and each port > + can access the Switch register space by configurting the PHY page. > + > + Each internal PHY might require calibration with the fused EFUSE on > + the switch exposed by the Airoha AN8855 SoC NVMEM. > + > +$ref: dsa.yaml# > + > +properties: > + compatible: > + const: airoha,an8855-switch > + > + reset-gpios: > + description: > + GPIO to be used to reset the whole device > + maxItems: 1 Since this affects the whole device, the SoC node (handled by the MFD driver) should handle it. Otherwise you expose the code to weird race conditions where one child MFD device resets the whole chip after the other MFD children have probed, and this undoes their settings. > + > + airoha,ext-surge: > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + Calibrate the internal PHY with the calibration values stored in EFUSE > + for the r50Ohm values. Doesn't seem that this pertains to the switch.
On Tue, Dec 10, 2024 at 10:48:55PM +0200, Vladimir Oltean wrote: > On Mon, Dec 09, 2024 at 02:44:20PM +0100, Christian Marangi wrote: > > Document support for Airoha AN8855 5-port Gigabit Switch. > > > > It does expose the 5 Internal PHYs on the MDIO bus and each port > > can access the Switch register space by configurting the PHY page. > > typo: configuring > Also below. > > > > > Each internal PHY might require calibration with the fused EFUSE on > > the switch exposed by the Airoha AN8855 SoC NVMEM. > > This paragraph should be irrelevant to the switch binding. > > > > > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> > > --- > > .../net/dsa/airoha,an8855-switch.yaml | 105 ++++++++++++++++++ > > MAINTAINERS | 1 + > > 2 files changed, 106 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml > > > > diff --git a/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml b/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml > > new file mode 100644 > > index 000000000000..63bcbebd6a29 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml > > @@ -0,0 +1,105 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/net/dsa/airoha,an8855-switch.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Airoha AN8855 Gigabit Switch > > + > > +maintainers: > > + - Christian Marangi <ansuelsmth@gmail.com> > > + > > +description: > > > + Airoha AN8855 is a 5-port Gigabit Switch. > > + > > + It does expose the 5 Internal PHYs on the MDIO bus and each port > > + can access the Switch register space by configurting the PHY page. > > + > > + Each internal PHY might require calibration with the fused EFUSE on > > + the switch exposed by the Airoha AN8855 SoC NVMEM. > > + > > +$ref: dsa.yaml# > > + > > +properties: > > + compatible: > > + const: airoha,an8855-switch > > + > > + reset-gpios: > > + description: > > + GPIO to be used to reset the whole device > > + maxItems: 1 > > Since this affects the whole device, the SoC node (handled by the > MFD driver) should handle it. Otherwise you expose the code to weird > race conditions where one child MFD device resets the whole chip after > the other MFD children have probed, and this undoes their settings. > OK. > > + > > + airoha,ext-surge: > > + $ref: /schemas/types.yaml#/definitions/flag > > + description: > > + Calibrate the internal PHY with the calibration values stored in EFUSE > > + for the r50Ohm values. > > Doesn't seem that this pertains to the switch. Do you think this should be placed in each PHY node? I wanted to prevent having to define a schema also for PHY if possible given how integrated these are. (originally it was defined in DT node to follow how it was done in Airoha SDK)
On Tue, Dec 10, 2024 at 09:59:04PM +0100, Christian Marangi wrote: > > > + airoha,ext-surge: > > > + $ref: /schemas/types.yaml#/definitions/flag > > > + description: > > > + Calibrate the internal PHY with the calibration values stored in EFUSE > > > + for the r50Ohm values. > > > > Doesn't seem that this pertains to the switch. > > Do you think this should be placed in each PHY node? Logically speaking, that's where it belongs. > I wanted to prevent having to define a schema also for PHY if possible > given how integrated these are. (originally it was defined in DT node > to follow how it was done in Airoha SDK) Does compatibility with the Airoha SDK dt-bindings matter in any way?
On Wed, Dec 11, 2024 at 12:16:02AM +0200, Vladimir Oltean wrote: > On Tue, Dec 10, 2024 at 09:59:04PM +0100, Christian Marangi wrote: > > > > + airoha,ext-surge: > > > > + $ref: /schemas/types.yaml#/definitions/flag > > > > + description: > > > > + Calibrate the internal PHY with the calibration values stored in EFUSE > > > > + for the r50Ohm values. > > > > > > Doesn't seem that this pertains to the switch. > > > > Do you think this should be placed in each PHY node? > > Logically speaking, that's where it belongs. > > > I wanted to prevent having to define a schema also for PHY if possible > > given how integrated these are. (originally it was defined in DT node > > to follow how it was done in Airoha SDK) > > Does compatibility with the Airoha SDK dt-bindings matter in any way? No it doesn't, the requirement for nvmem already deviates a lot so changes are needed anyway.
diff --git a/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml b/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml new file mode 100644 index 000000000000..63bcbebd6a29 --- /dev/null +++ b/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/dsa/airoha,an8855-switch.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha AN8855 Gigabit Switch + +maintainers: + - Christian Marangi <ansuelsmth@gmail.com> + +description: > + Airoha AN8855 is a 5-port Gigabit Switch. + + It does expose the 5 Internal PHYs on the MDIO bus and each port + can access the Switch register space by configurting the PHY page. + + Each internal PHY might require calibration with the fused EFUSE on + the switch exposed by the Airoha AN8855 SoC NVMEM. + +$ref: dsa.yaml# + +properties: + compatible: + const: airoha,an8855-switch + + reset-gpios: + description: + GPIO to be used to reset the whole device + maxItems: 1 + + airoha,ext-surge: + $ref: /schemas/types.yaml#/definitions/flag + description: + Calibrate the internal PHY with the calibration values stored in EFUSE + for the r50Ohm values. + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + ethernet-switch { + compatible = "airoha,an8855-switch"; + reset-gpios = <&pio 39 0>; + + airoha,ext-surge; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + phy-mode = "internal"; + phy-handle = <&internal_phy1>; + }; + + port@1 { + reg = <1>; + label = "lan2"; + phy-mode = "internal"; + phy-handle = <&internal_phy2>; + }; + + port@2 { + reg = <2>; + label = "lan3"; + phy-mode = "internal"; + phy-handle = <&internal_phy3>; + }; + + port@3 { + reg = <3>; + label = "lan4"; + phy-mode = "internal"; + phy-handle = <&internal_phy4>; + }; + + port@4 { + reg = <4>; + label = "wan"; + phy-mode = "internal"; + phy-handle = <&internal_phy5>; + }; + + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index e3569fe5f3de..fd37e829fab5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -718,6 +718,7 @@ L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) L: netdev@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/net/airoha,an8855-mdio.yaml +F: Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml F: Documentation/devicetree/bindings/nvmem/airoha,an8855-efuse.yaml AIROHA ETHERNET DRIVER
Document support for Airoha AN8855 5-port Gigabit Switch. It does expose the 5 Internal PHYs on the MDIO bus and each port can access the Switch register space by configurting the PHY page. Each internal PHY might require calibration with the fused EFUSE on the switch exposed by the Airoha AN8855 SoC NVMEM. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> --- .../net/dsa/airoha,an8855-switch.yaml | 105 ++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 106 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml