| Message ID | 20241226063313.3267515-5-damon.ding@rock-chips.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add eDP support for RK3588 | expand |
On Thu, Dec 26, 2024 at 02:33:00PM +0800, Damon Ding wrote: > According to the datasheet, setting the dig_clk_sel bit of CMN_REG(0097) > to 1'b1 selects LCPLL as the reference clock, while setting it to 1'b0 > selects the ROPLL. > > Signed-off-by: Damon Ding <damon.ding@rock-chips.com> > --- > drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c index ceab9c71d3b5..0fecbb1df6fb 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -94,8 +94,8 @@ #define LCPLL_ALONE_MODE BIT(1) /* CMN_REG(0097) */ #define DIG_CLK_SEL BIT(1) -#define ROPLL_REF BIT(1) -#define LCPLL_REF 0 +#define LCPLL_REF BIT(1) +#define ROPLL_REF 0 /* CMN_REG(0099) */ #define CMN_ROPLL_ALONE_MODE BIT(2) #define ROPLL_ALONE_MODE BIT(2)
According to the datasheet, setting the dig_clk_sel bit of CMN_REG(0097) to 1'b1 selects LCPLL as the reference clock, while setting it to 1'b0 selects the ROPLL. Signed-off-by: Damon Ding <damon.ding@rock-chips.com> --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)