| Message ID | 20241230214445.27602-8-alejandro.lucero-palau@amd.com |
|---|---|
| State | New |
| Headers | show |
| Series | cxl: add type2 device basic support | expand |
On Mon, 30 Dec 2024 21:44:25 +0000 alejandro.lucero-palau@amd.com wrote: > From: Alejandro Lucero <alucerop@amd.com> > > Use cxl code for registers discovery and mapping. > > Validate capabilities found based on those registers against expected > capabilities. > > Signed-off-by: Alejandro Lucero <alucerop@amd.com> > Reviewed-by: Martin Habets <habetsm.xilinx@gmail.com> > Reviewed-by: Zhi Wang <zhi@nvidia.com> > Acked-by: Edward Cree <ecree.xilinx@gmail.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
alejandro.lucero-palau@ wrote: > From: Alejandro Lucero <alucerop@amd.com> > > Use cxl code for registers discovery and mapping. > > Validate capabilities found based on those registers against expected > capabilities. > > Signed-off-by: Alejandro Lucero <alucerop@amd.com> > Reviewed-by: Martin Habets <habetsm.xilinx@gmail.com> > Reviewed-by: Zhi Wang <zhi@nvidia.com> > Acked-by: Edward Cree <ecree.xilinx@gmail.com> > --- > drivers/net/ethernet/sfc/efx_cxl.c | 21 +++++++++++++++++++++ > 1 file changed, 21 insertions(+) > > diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c > index 12c9d50cbb26..29368d010adc 100644 > --- a/drivers/net/ethernet/sfc/efx_cxl.c > +++ b/drivers/net/ethernet/sfc/efx_cxl.c > @@ -22,6 +22,8 @@ int efx_cxl_init(struct efx_probe_data *probe_data) > { > struct efx_nic *efx = &probe_data->efx; > struct pci_dev *pci_dev = efx->pci_dev; > + DECLARE_BITMAP(expected, CXL_MAX_CAPS); > + DECLARE_BITMAP(found, CXL_MAX_CAPS); > struct efx_cxl *cxl; > struct resource res; > u16 dvsec; > @@ -64,6 +66,25 @@ int efx_cxl_init(struct efx_probe_data *probe_data) > goto err_resource_set; > } > > + rc = cxl_pci_accel_setup_regs(pci_dev, cxl->cxlds); > + if (rc) { > + pci_err(pci_dev, "CXL accel setup regs failed"); > + goto err_resource_set; > + } > + > + bitmap_clear(expected, 0, CXL_MAX_CAPS); > + set_bit(CXL_DEV_CAP_HDM, expected); > + set_bit(CXL_DEV_CAP_HDM, expected); > + set_bit(CXL_DEV_CAP_RAS, expected); > + > + if (!cxl_pci_check_caps(cxl->cxlds, expected, found)) { > + pci_err(pci_dev, > + "CXL device capabilities found(%pb) not as expected(%pb)", > + found, expected); > + rc = -EIO; > + goto err_resource_set; > + } > + Walk the existing valid bits in the reg maps. If you want to do this with bitmaps you can convert reg_map valid bits into a bitmap locally, but that redundant infrastructure can be left out of the core.
On 1/18/25 01:53, Dan Williams wrote: > alejandro.lucero-palau@ wrote: >> From: Alejandro Lucero <alucerop@amd.com> >> >> Use cxl code for registers discovery and mapping. >> >> Validate capabilities found based on those registers against expected >> capabilities. >> >> Signed-off-by: Alejandro Lucero <alucerop@amd.com> >> Reviewed-by: Martin Habets <habetsm.xilinx@gmail.com> >> Reviewed-by: Zhi Wang <zhi@nvidia.com> >> Acked-by: Edward Cree <ecree.xilinx@gmail.com> >> --- >> drivers/net/ethernet/sfc/efx_cxl.c | 21 +++++++++++++++++++++ >> 1 file changed, 21 insertions(+) >> >> diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c >> index 12c9d50cbb26..29368d010adc 100644 >> --- a/drivers/net/ethernet/sfc/efx_cxl.c >> +++ b/drivers/net/ethernet/sfc/efx_cxl.c >> @@ -22,6 +22,8 @@ int efx_cxl_init(struct efx_probe_data *probe_data) >> { >> struct efx_nic *efx = &probe_data->efx; >> struct pci_dev *pci_dev = efx->pci_dev; >> + DECLARE_BITMAP(expected, CXL_MAX_CAPS); >> + DECLARE_BITMAP(found, CXL_MAX_CAPS); >> struct efx_cxl *cxl; >> struct resource res; >> u16 dvsec; >> @@ -64,6 +66,25 @@ int efx_cxl_init(struct efx_probe_data *probe_data) >> goto err_resource_set; >> } >> >> + rc = cxl_pci_accel_setup_regs(pci_dev, cxl->cxlds); >> + if (rc) { >> + pci_err(pci_dev, "CXL accel setup regs failed"); >> + goto err_resource_set; >> + } >> + >> + bitmap_clear(expected, 0, CXL_MAX_CAPS); >> + set_bit(CXL_DEV_CAP_HDM, expected); >> + set_bit(CXL_DEV_CAP_HDM, expected); >> + set_bit(CXL_DEV_CAP_RAS, expected); >> + >> + if (!cxl_pci_check_caps(cxl->cxlds, expected, found)) { >> + pci_err(pci_dev, >> + "CXL device capabilities found(%pb) not as expected(%pb)", >> + found, expected); >> + rc = -EIO; >> + goto err_resource_set; >> + } >> + > Walk the existing valid bits in the reg maps. If you want to do this > with bitmaps you can convert reg_map valid bits into a bitmap locally, > but that redundant infrastructure can be left out of the core. This is the accel driver. Some way for doing this needs to be implemented, and although I'm not against solving the duplication between the reg_map valid bit and the new capability bitmap, an accel driver will need this piece of code or something equivalent.
diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c index 12c9d50cbb26..29368d010adc 100644 --- a/drivers/net/ethernet/sfc/efx_cxl.c +++ b/drivers/net/ethernet/sfc/efx_cxl.c @@ -22,6 +22,8 @@ int efx_cxl_init(struct efx_probe_data *probe_data) { struct efx_nic *efx = &probe_data->efx; struct pci_dev *pci_dev = efx->pci_dev; + DECLARE_BITMAP(expected, CXL_MAX_CAPS); + DECLARE_BITMAP(found, CXL_MAX_CAPS); struct efx_cxl *cxl; struct resource res; u16 dvsec; @@ -64,6 +66,25 @@ int efx_cxl_init(struct efx_probe_data *probe_data) goto err_resource_set; } + rc = cxl_pci_accel_setup_regs(pci_dev, cxl->cxlds); + if (rc) { + pci_err(pci_dev, "CXL accel setup regs failed"); + goto err_resource_set; + } + + bitmap_clear(expected, 0, CXL_MAX_CAPS); + set_bit(CXL_DEV_CAP_HDM, expected); + set_bit(CXL_DEV_CAP_HDM, expected); + set_bit(CXL_DEV_CAP_RAS, expected); + + if (!cxl_pci_check_caps(cxl->cxlds, expected, found)) { + pci_err(pci_dev, + "CXL device capabilities found(%pb) not as expected(%pb)", + found, expected); + rc = -EIO; + goto err_resource_set; + } + probe_data->cxl = cxl; return 0;