| Message ID | 20250106053358.21664-5-shubhrajyoti.datta@amd.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | EDAC: Versal NET: Add support for error notification | expand |
On Mon, Jan 06, 2025 at 11:03:57AM +0530, Shubhrajyoti Datta wrote: > +description: > + The integrated DDR Memory Controllers (DDRMCs) support both DDR5 and LPDDR5 > + compact and extended memory interfaces. Versal NET DDR memory controller > + has an optional ECC support which correct single bit ECC errors and detect > + double bit ECC errors. It also has support for reporting other errors like > + MMCM (Mixed-Mode Clock Manager) errors and General software errors. > + > +properties: > + compatible: > + const: amd,versal-net-ddrmc5 git grep amd,versal-net - 0 results Where is your soc? > + > + amd,rproc: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + phandle to the remoteproc_r5 rproc node using which APU interacts > + with remote processor. APU primarily communicates with the RPU for > + accessing the DDRMC address space and getting error notification. > + > +required: > + - compatible > + - amd,rproc > + > +additionalProperties: false > + > +examples: > + - | > + memory-controller { > + compatible = "amd,versal-net-ddrmc5"; Still wrong indentation. I commented on wrong alignment so that's on me. Use 4 spaces for example indentation. (or 2 spaces, but not three... there are no bindings like that).
On 1/7/25 07:37, Krzysztof Kozlowski wrote: > On Mon, Jan 06, 2025 at 11:03:57AM +0530, Shubhrajyoti Datta wrote: >> +description: >> + The integrated DDR Memory Controllers (DDRMCs) support both DDR5 and LPDDR5 >> + compact and extended memory interfaces. Versal NET DDR memory controller >> + has an optional ECC support which correct single bit ECC errors and detect >> + double bit ECC errors. It also has support for reporting other errors like >> + MMCM (Mixed-Mode Clock Manager) errors and General software errors. >> + >> +properties: >> + compatible: >> + const: amd,versal-net-ddrmc5 > > git grep amd,versal-net - 0 results > > Where is your soc? Actually it should be still branded as xlnx,versal-net to follow the same pattern for other drivers. And likely pattern should be also listed in Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml Thanks, Michal
diff --git a/Documentation/devicetree/bindings/memory-controllers/amd,versal-net-ddrmc5.yaml b/Documentation/devicetree/bindings/memory-controllers/amd,versal-net-ddrmc5.yaml new file mode 100644 index 000000000000..7021449e2211 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/amd,versal-net-ddrmc5.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/amd,versal-net-ddrmc5.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Versal NET Memory Controller + +maintainers: + - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> + +description: + The integrated DDR Memory Controllers (DDRMCs) support both DDR5 and LPDDR5 + compact and extended memory interfaces. Versal NET DDR memory controller + has an optional ECC support which correct single bit ECC errors and detect + double bit ECC errors. It also has support for reporting other errors like + MMCM (Mixed-Mode Clock Manager) errors and General software errors. + +properties: + compatible: + const: amd,versal-net-ddrmc5 + + amd,rproc: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to the remoteproc_r5 rproc node using which APU interacts + with remote processor. APU primarily communicates with the RPU for + accessing the DDRMC address space and getting error notification. + +required: + - compatible + - amd,rproc + +additionalProperties: false + +examples: + - | + memory-controller { + compatible = "amd,versal-net-ddrmc5"; + amd,rproc = <&remoteproc_r5>; + };
Add device tree bindings for AMD Versal NET EDAC for DDR controller. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> --- Changes in v5: Update the binding Wrap the description Changes in v4: Update the compatible align the example Enhance the description for rproc Changes in v2: - rename EDAC to memory controller - update the compatible name - Add remote proc handle - Read the data width from the registers - Remove the dwidth, rank and channel number the same is read from the RpMsg. .../amd,versal-net-ddrmc5.yaml | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/amd,versal-net-ddrmc5.yaml