| Message ID | 20250115153019.407646-3-sergio.paracuellos@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | mips: dts: ralink: update system controller nodes and its consumers | expand |
On 15/01/2025 16:30, Sergio Paracuellos wrote: > Current RT2880 device tree file is out of date and must be merged with real > device tree file used in openWRT project [0]. As a first iteration for this No, that's not the reason. Whatever forks have, is their problem. The reason is that you are improving or adding here missing bits but each bit must be justified. Again: whatever is in OpenWRT is not justification. Justification is that device is like this, SoC is like that or DTS is written not according to bindings. > changes, align the current file with the needed changes for system controller Please wrap commit message according to Linux coding style / submission process (neither too early nor over the limit): https://elixir.bootlin.com/linux/v6.4-rc1/source/Documentation/process/submitting-patches.rst#L597 > from '6f3b15586eef ("clk: ralink: add clock and reset driver for MTMIPS SoCs")'. Use proper commit syntax. '' are wrong, missing commit word. > > [0]: https://github.com/openwrt/openwrt/blob/main/target/linux/ramips/dts/rt2880.dtsi > > Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> > --- > arch/mips/boot/dts/ralink/rt2880.dtsi | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/arch/mips/boot/dts/ralink/rt2880.dtsi b/arch/mips/boot/dts/ralink/rt2880.dtsi > index 8fc1987d9063..1f2ea3434324 100644 > --- a/arch/mips/boot/dts/ralink/rt2880.dtsi > +++ b/arch/mips/boot/dts/ralink/rt2880.dtsi > @@ -1,4 +1,6 @@ > // SPDX-License-Identifier: GPL-2.0 > +#include <dt-bindings/clock/mediatek,mtmips-sysc.h> > + > / { > #address-cells = <1>; > #size-cells = <1>; > @@ -25,9 +27,11 @@ palmbus@300000 { > #address-cells = <1>; > #size-cells = <1>; > > - sysc@0 { > - compatible = "ralink,rt2880-sysc"; > + sysc: syscon@0 { > + compatible = "ralink,rt2880-sysc", "syscon"; > reg = <0x0 0x100>; > + #clock-cells = <1>; > + #reset-cells = <1>; Nothing from here is explained in commit msg. Why this is suddenly clock and reset controller? > }; > Best regards, Krzysztof
On Thu, Jan 16, 2025 at 10:19 AM Krzysztof Kozlowski <krzk@kernel.org> wrote: > > On 15/01/2025 16:30, Sergio Paracuellos wrote: > > Current RT2880 device tree file is out of date and must be merged with real > > device tree file used in openWRT project [0]. As a first iteration for this > > No, that's not the reason. Whatever forks have, is their problem. The > reason is that you are improving or adding here missing bits but each > bit must be justified. Again: whatever is in OpenWRT is not > justification. Justification is that device is like this, SoC is like > that or DTS is written not according to bindings. Ok, I will clarify that the DTs is not currently written according to bindings. > > > changes, align the current file with the needed changes for system controller > > Please wrap commit message according to Linux coding style / submission > process (neither too early nor over the limit): > https://elixir.bootlin.com/linux/v6.4-rc1/source/Documentation/process/submitting-patches.rst#L597 I did not want to cut the hash and commit message for the driver submission so this line become a bit longer than usual. But other times with warning messages or message lines like this I thought readability was preferred to match width for the message itself... Am I wrong? > > > from '6f3b15586eef ("clk: ralink: add clock and reset driver for MTMIPS SoCs")'. > > Use proper commit syntax. '' are wrong, missing commit word. Checkpatch only complained if no start and end single quotes are present so I thought the 'commit' message word was not necessary. Will add it, thanks. > > > > > [0]: https://github.com/openwrt/openwrt/blob/main/target/linux/ramips/dts/rt2880.dtsi > > > > Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> > > --- > > arch/mips/boot/dts/ralink/rt2880.dtsi | 10 ++++++++-- > > 1 file changed, 8 insertions(+), 2 deletions(-) > > > > diff --git a/arch/mips/boot/dts/ralink/rt2880.dtsi b/arch/mips/boot/dts/ralink/rt2880.dtsi > > index 8fc1987d9063..1f2ea3434324 100644 > > --- a/arch/mips/boot/dts/ralink/rt2880.dtsi > > +++ b/arch/mips/boot/dts/ralink/rt2880.dtsi > > @@ -1,4 +1,6 @@ > > // SPDX-License-Identifier: GPL-2.0 > > +#include <dt-bindings/clock/mediatek,mtmips-sysc.h> > > + > > / { > > #address-cells = <1>; > > #size-cells = <1>; > > @@ -25,9 +27,11 @@ palmbus@300000 { > > #address-cells = <1>; > > #size-cells = <1>; > > > > - sysc@0 { > > - compatible = "ralink,rt2880-sysc"; > > + sysc: syscon@0 { > > + compatible = "ralink,rt2880-sysc", "syscon"; > > reg = <0x0 0x100>; > > + #clock-cells = <1>; > > + #reset-cells = <1>; > > Nothing from here is explained in commit msg. Why this is suddenly clock > and reset controller? To match current binding, will add this too to the commit message. > > > }; > > > > > Best regards, > Krzysztof Thanks, Sergio Paracuellos
diff --git a/arch/mips/boot/dts/ralink/rt2880.dtsi b/arch/mips/boot/dts/ralink/rt2880.dtsi index 8fc1987d9063..1f2ea3434324 100644 --- a/arch/mips/boot/dts/ralink/rt2880.dtsi +++ b/arch/mips/boot/dts/ralink/rt2880.dtsi @@ -1,4 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 +#include <dt-bindings/clock/mediatek,mtmips-sysc.h> + / { #address-cells = <1>; #size-cells = <1>; @@ -25,9 +27,11 @@ palmbus@300000 { #address-cells = <1>; #size-cells = <1>; - sysc@0 { - compatible = "ralink,rt2880-sysc"; + sysc: syscon@0 { + compatible = "ralink,rt2880-sysc", "syscon"; reg = <0x0 0x100>; + #clock-cells = <1>; + #reset-cells = <1>; }; intc: intc@200 { @@ -50,6 +54,8 @@ uartlite@c00 { compatible = "ralink,rt2880-uart", "ns16550a"; reg = <0xc00 0x100>; + clocks = <&sysc RT2880_CLK_UARTLITE>; + interrupt-parent = <&intc>; interrupts = <8>;
Current RT2880 device tree file is out of date and must be merged with real device tree file used in openWRT project [0]. As a first iteration for this changes, align the current file with the needed changes for system controller from '6f3b15586eef ("clk: ralink: add clock and reset driver for MTMIPS SoCs")'. [0]: https://github.com/openwrt/openwrt/blob/main/target/linux/ramips/dts/rt2880.dtsi Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> --- arch/mips/boot/dts/ralink/rt2880.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-)