| Message ID | 20250120094715.25802-2-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Add Support for RZ/G3E ICU | expand |
Hi Biju, Thanks for your patch! > From: Biju Das <biju.das.jz@bp.renesas.com> > Sent: 20 January 2025 09:47 > Subject: [PATCH 01/11] dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E SoC > > Document RZ/G3E (R9A09G047) ICU bindings. The ICU block on the RZ/G3E > SoC is almost identical to the one found on the RZ/V2H SoC, with the > following differences: > - The TINT register offset is 0x830 compared to ox30 on RZ/V2H. > - The number of supported GPIO interrupts for TINT selection is 141 > instead of 86. > - The pin index and TINT selection index are not in the 1:1 map > - The number of TSSR registers is 15 instead of 8 > - Each TSSR register can program 2 TINTs instead of 4 TINTs > > Hence new compatible string "renesas,r9a09g047-icu" is added for RZ/G3E > SoC. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Cheers, Fab > --- > .../bindings/interrupt-controller/renesas,rzv2h-icu.yaml | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml > b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml > index d7ef4f1323a7..3f99c8645767 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml > +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml > @@ -4,7 +4,7 @@ > $id: http://devicetree.org/schemas/interrupt-controller/renesas,rzv2h-icu.yaml# > $schema: http://devicetree.org/meta-schemas/core.yaml# > > -title: Renesas RZ/V2H(P) Interrupt Control Unit > +title: Renesas RZ/{G3E,V2H(P)} Interrupt Control Unit > > maintainers: > - Fabrizio Castro <fabrizio.castro.jz@renesas.com> > @@ -20,7 +20,9 @@ description: > > properties: > compatible: > - const: renesas,r9a09g057-icu # RZ/V2H(P) > + enum: > + - renesas,r9a09g047-icu # RZ/G3E > + - renesas,r9a09g057-icu # RZ/V2H(P) > > '#interrupt-cells': > description: The first cell is the SPI number of the NMI or the > -- > 2.43.0
On Mon, 20 Jan 2025 09:46:57 +0000, Biju Das wrote: > Document RZ/G3E (R9A09G047) ICU bindings. The ICU block on the RZ/G3E > SoC is almost identical to the one found on the RZ/V2H SoC, with the > following differences: > - The TINT register offset is 0x830 compared to ox30 on RZ/V2H. > - The number of supported GPIO interrupts for TINT selection is 141 > instead of 86. > - The pin index and TINT selection index are not in the 1:1 map > - The number of TSSR registers is 15 instead of 8 > - Each TSSR register can program 2 TINTs instead of 4 TINTs > > Hence new compatible string "renesas,r9a09g047-icu" is added for RZ/G3E > SoC. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > --- > .../bindings/interrupt-controller/renesas,rzv2h-icu.yaml | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > Acked-by: Rob Herring (Arm) <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml index d7ef4f1323a7..3f99c8645767 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/interrupt-controller/renesas,rzv2h-icu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas RZ/V2H(P) Interrupt Control Unit +title: Renesas RZ/{G3E,V2H(P)} Interrupt Control Unit maintainers: - Fabrizio Castro <fabrizio.castro.jz@renesas.com> @@ -20,7 +20,9 @@ description: properties: compatible: - const: renesas,r9a09g057-icu # RZ/V2H(P) + enum: + - renesas,r9a09g047-icu # RZ/G3E + - renesas,r9a09g057-icu # RZ/V2H(P) '#interrupt-cells': description: The first cell is the SPI number of the NMI or the
Document RZ/G3E (R9A09G047) ICU bindings. The ICU block on the RZ/G3E SoC is almost identical to the one found on the RZ/V2H SoC, with the following differences: - The TINT register offset is 0x830 compared to ox30 on RZ/V2H. - The number of supported GPIO interrupts for TINT selection is 141 instead of 86. - The pin index and TINT selection index are not in the 1:1 map - The number of TSSR registers is 15 instead of 8 - Each TSSR register can program 2 TINTs instead of 4 TINTs Hence new compatible string "renesas,r9a09g047-icu" is added for RZ/G3E SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- .../bindings/interrupt-controller/renesas,rzv2h-icu.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)