| Message ID | 20250120094715.25802-10-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Add Support for RZ/G3E ICU | expand |
Hi Biju, Thanks for your patch! > From: Biju Das <biju.das.jz@bp.renesas.com> > Sent: 20 January 2025 09:47 > Subject: [PATCH 09/11] irqchip/renesas-rzv2h: Add tien variable to struct rzv2h_hw_info > > The TINT enable position on RZ/G3E is BIT 15 compared to BIT 8 on RZ/V2H. > Add tien variable to struct rzv2h_hw_info to simplify the calculations > when we add support for RZ/G3E and drop the macro ICU_TSSR_TIEN. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Cheers, Fab > --- > drivers/irqchip/irq-renesas-rzv2h.c | 11 ++++++----- > 1 file changed, 6 insertions(+), 5 deletions(-) > > diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c > index 5990dcf72ef0..a1ca34d33c93 100644 > --- a/drivers/irqchip/irq-renesas-rzv2h.c > +++ b/drivers/irqchip/irq-renesas-rzv2h.c > @@ -64,8 +64,6 @@ > #define ICU_TINT_LEVEL_HIGH 2 > #define ICU_TINT_LEVEL_LOW 3 > > -#define ICU_TSSR_TIEN(n) (BIT(7) << ((n) * 8)) > - > #define ICU_TITSR_K(tint_nr) ((tint_nr) / 16) > #define ICU_TITSR_TITSEL_N(tint_nr) ((tint_nr) % 16) > #define ICU_TITSR_TITSEL_PREP(titsel, n) ICU_IITSR_IITSEL_PREP(titsel, n) > @@ -78,6 +76,7 @@ > /** > * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure. > * @t_offs: TINT offset > + * @tien: TIEN mask > * @tssel_mask: TSSEL mask > * @tssel_shift: TSSEL shift > * @max_tssel: TSSEL max value > @@ -85,6 +84,7 @@ > */ > struct rzv2h_hw_info { > u16 t_offs; > + u16 tien; > u16 tssel_mask; > u8 tssel_shift; > u8 max_tssel; > @@ -152,9 +152,9 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable) > guard(raw_spinlock)(&priv->lock); > tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(k)); > if (enable) > - tssr |= ICU_TSSR_TIEN(tssel_n); > + tssr |= priv->info->tien << (tssel_n * priv->info->tssel_shift); > else > - tssr &= ~ICU_TSSR_TIEN(tssel_n); > + tssr &= ~(priv->info->tien << (tssel_n * priv->info->tssel_shift)); > writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(k)); > } > > @@ -314,7 +314,7 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) > > titsr_k = ICU_TITSR_K(tint_nr); > titsel_n = ICU_TITSR_TITSEL_N(tint_nr); > - tien = ICU_TSSR_TIEN(titsel_n); > + tien = priv->info->tien << (titsel_n * priv->info->tssel_shift); > > guard(raw_spinlock)(&priv->lock); > > @@ -517,6 +517,7 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p > static const struct rzv2h_hw_info rzv2h_hw_params = { > .t_offs = 0, > .max_tssel = 0x55, > + .tien = BIT(7), > .tssel_mask = GENMASK(6, 0), > .tssel_shift = 8, > .tssr_k = 4, > -- > 2.43.0 >
diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index 5990dcf72ef0..a1ca34d33c93 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -64,8 +64,6 @@ #define ICU_TINT_LEVEL_HIGH 2 #define ICU_TINT_LEVEL_LOW 3 -#define ICU_TSSR_TIEN(n) (BIT(7) << ((n) * 8)) - #define ICU_TITSR_K(tint_nr) ((tint_nr) / 16) #define ICU_TITSR_TITSEL_N(tint_nr) ((tint_nr) % 16) #define ICU_TITSR_TITSEL_PREP(titsel, n) ICU_IITSR_IITSEL_PREP(titsel, n) @@ -78,6 +76,7 @@ /** * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure. * @t_offs: TINT offset + * @tien: TIEN mask * @tssel_mask: TSSEL mask * @tssel_shift: TSSEL shift * @max_tssel: TSSEL max value @@ -85,6 +84,7 @@ */ struct rzv2h_hw_info { u16 t_offs; + u16 tien; u16 tssel_mask; u8 tssel_shift; u8 max_tssel; @@ -152,9 +152,9 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable) guard(raw_spinlock)(&priv->lock); tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(k)); if (enable) - tssr |= ICU_TSSR_TIEN(tssel_n); + tssr |= priv->info->tien << (tssel_n * priv->info->tssel_shift); else - tssr &= ~ICU_TSSR_TIEN(tssel_n); + tssr &= ~(priv->info->tien << (tssel_n * priv->info->tssel_shift)); writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(k)); } @@ -314,7 +314,7 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) titsr_k = ICU_TITSR_K(tint_nr); titsel_n = ICU_TITSR_TITSEL_N(tint_nr); - tien = ICU_TSSR_TIEN(titsel_n); + tien = priv->info->tien << (titsel_n * priv->info->tssel_shift); guard(raw_spinlock)(&priv->lock); @@ -517,6 +517,7 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p static const struct rzv2h_hw_info rzv2h_hw_params = { .t_offs = 0, .max_tssel = 0x55, + .tien = BIT(7), .tssel_mask = GENMASK(6, 0), .tssel_shift = 8, .tssr_k = 4,
The TINT enable position on RZ/G3E is BIT 15 compared to BIT 8 on RZ/V2H. Add tien variable to struct rzv2h_hw_info to simplify the calculations when we add support for RZ/G3E and drop the macro ICU_TSSR_TIEN. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/irqchip/irq-renesas-rzv2h.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-)