| Message ID | 20250123170508.13578-9-john.madieu.xa@bp.renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Commit | b19b2c9c645e807a6711c77165171d97bbbcdaad |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | soc: renesas: Add RZ/G3E SoC detection support | expand |
Hi John, On Thu, Jan 23, 2025 at 6:06 PM John Madieu <john.madieu.xa@bp.renesas.com> wrote: > Add system controller node to RZ/G3E (R9A09G047) SoC DTSI, as it is also > required for SoC identification > > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> Thanks for your patch! > --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi > +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi > @@ -162,6 +162,13 @@ cpg: clock-controller@10420000 { > #power-domain-cells = <0>; > }; > > + sys: system-controller@10430000 { > + compatible = "renesas,r9a09g047-sys"; > + reg = <0 0x10430000 0 0x10000>; > + clocks = <&cpg CPG_CORE R9A09G047_SYS_0_PCLK>; > + resets = <&cpg 0x30>; > + }; > + > ostm0: timer@11800000 { The patch adding the OSTM node hasn't been applied or even submitted yet ;-) But I can handle... > compatible = "renesas,r9a09g047-ostm", "renesas,ostm"; > reg = <0x0 0x11800000 0x0 0x1000>; Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v6.15. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
> -----Original Message----- > From: Geert Uytterhoeven <geert@linux-m68k.org> > Sent: Friday, January 24, 2025 3:25 PM > Subject: Re: [PATCH v4 8/9] arm64: dts: renesas: r9a09g047: Add sys node > Hi Geert, Thanks for your review. > Hi John, > > On Thu, Jan 23, 2025 at 6:06 PM John Madieu > <john.madieu.xa@bp.renesas.com> wrote: > > Add system controller node to RZ/G3E (R9A09G047) SoC DTSI, as it is > > also required for SoC identification > > > > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> > > Thanks for your patch! > > > --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi > > +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi > > @@ -162,6 +162,13 @@ cpg: clock-controller@10420000 { > > #power-domain-cells = <0>; > > }; > > > > + sys: system-controller@10430000 { > > + compatible = "renesas,r9a09g047-sys"; > > + reg = <0 0x10430000 0 0x10000>; > > + clocks = <&cpg CPG_CORE R9A09G047_SYS_0_PCLK>; > > + resets = <&cpg 0x30>; > > + }; > > + > > ostm0: timer@11800000 { > > The patch adding the OSTM node hasn't been applied or even submitted yet > ;-) But I can handle... Thanks for handling this. > > > compatible = "renesas,r9a09g047-ostm", > "renesas,ostm"; > > reg = <0x0 0x11800000 0x0 0x1000>; > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue > in renesas-devel for v6.15. > > Gr{oetje,eeting}s, > > Geert Regards, John
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index 444fadaf7254..0840450dda47 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -162,6 +162,13 @@ cpg: clock-controller@10420000 { #power-domain-cells = <0>; }; + sys: system-controller@10430000 { + compatible = "renesas,r9a09g047-sys"; + reg = <0 0x10430000 0 0x10000>; + clocks = <&cpg CPG_CORE R9A09G047_SYS_0_PCLK>; + resets = <&cpg 0x30>; + }; + ostm0: timer@11800000 { compatible = "renesas,r9a09g047-ostm", "renesas,ostm"; reg = <0x0 0x11800000 0x0 0x1000>;
Add system controller node to RZ/G3E (R9A09G047) SoC DTSI, as it is also required for SoC identification Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> --- Changes: v1 -> v2: No changes v2 -> v3: No changes v3 -> v4: No changes arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)