| Message ID | 20250128172917.4565-2-u.kleine-koenig@baylibre.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [RESEND] ARM: dts: socfpga: Add basic support for Terrasic's de10-nano | expand |
> +&gmac1 { > + /* Uses a KSZ9031RNX phy */ > + status = "okay"; > + phy-mode = "rgmii"; > + > + rxd0-skew-ps = <420>; > + rxd1-skew-ps = <420>; > + rxd2-skew-ps = <420>; > + rxd3-skew-ps = <420>; > + txen-skew-ps = <0>; > + txc-skew-ps = <1860>; > + rxdv-skew-ps = <420>; > + rxc-skew-ps = <1680>; > +}; Hi Uwe The convectional meaning of phy-mode 'rgmii' is that the PCB provides the 2ns delay. Here you are abusing the > + txc-skew-ps = <1860>; > + rxc-skew-ps = <1680>; To add these delays. Please test without these two lines, and change phy-mode to 'rgmii-id'. 1680 is rather low, so it might not work. Look for CRC errors for received packets. Andrew
Hello Andrew, On Tue, Jan 28, 2025 at 06:44:26PM +0100, Andrew Lunn wrote: > > +&gmac1 { > > + /* Uses a KSZ9031RNX phy */ > > + status = "okay"; > > + phy-mode = "rgmii"; > > + > > + rxd0-skew-ps = <420>; > > + rxd1-skew-ps = <420>; > > + rxd2-skew-ps = <420>; > > + rxd3-skew-ps = <420>; > > + txen-skew-ps = <0>; > > + txc-skew-ps = <1860>; > > + rxdv-skew-ps = <420>; > > + rxc-skew-ps = <1680>; > > +}; > > The convectional meaning of phy-mode 'rgmii' is that the PCB provides > the 2ns delay. Here you are abusing the > > > + txc-skew-ps = <1860>; > > + rxc-skew-ps = <1680>; > > To add these delays. Ah, at some point I already knew that. Thanks for repeating that hint. (Back then it was for arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts.) > Please test without these two lines, and change phy-mode to > 'rgmii-id'. 1680 is rather low, so it might not work. Look for CRC > errors for received packets. I did an apt upgrade involving > 100 MB downloads with rgmii-id and afterwards I had: # ip -stats link show dev eth0 2: eth0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAU LT group default qlen 1000 link/ether ee:5f:09:22:72:da brd ff:ff:ff:ff:ff:ff RX: bytes packets errors dropped missed mcast 158336739 113000 0 0 0 0 TX: bytes packets errors dropped carrier collsns 482481 5094 0 0 0 0 so that seems to be fine, right? Best regards Uwe
On 28/01/2025 18:29, Uwe Kleine-König wrote: > This dts is enough to make the board boot to Linux with the rootfs on > a micro SD card. > > Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> > --- > Hello, > > in the variant I sent 15 min ago I fatfingered the address of the > linux-arm-kernel list. So here comes a resend with the right address ... > > Sorry for the noise > Uwe > > arch/arm/boot/dts/intel/socfpga/Makefile | 1 + > .../socfpga/socfpga_cyclone5_de10nano.dts | 90 +++++++++++++++++++ > 2 files changed, 91 insertions(+) > create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dts > > diff --git a/arch/arm/boot/dts/intel/socfpga/Makefile b/arch/arm/boot/dts/intel/socfpga/Makefile > index c467828aeb4b..7f69a0355ea5 100644 > --- a/arch/arm/boot/dts/intel/socfpga/Makefile > +++ b/arch/arm/boot/dts/intel/socfpga/Makefile > @@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \ > socfpga_cyclone5_mcvevk.dtb \ > socfpga_cyclone5_socdk.dtb \ > socfpga_cyclone5_de0_nano_soc.dtb \ > + socfpga_cyclone5_de10nano.dtb \ > socfpga_cyclone5_sockit.dtb \ > socfpga_cyclone5_socrates.dtb \ > socfpga_cyclone5_sodia.dtb \ > diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dts > new file mode 100644 > index 000000000000..d1f23a57a94d > --- /dev/null > +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dts > @@ -0,0 +1,90 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (C) 2017, Intel Corporation > + * > + * based on socfpga_cyclone5_de0_nano_soc.dts > + */ > +/dts-v1/; > + > +#include "socfpga_cyclone5.dtsi" > +#include <dt-bindings/interrupt-controller/irq.h> > +#include <dt-bindings/gpio/gpio.h> > + > +/ { > + model = "Terasic DE10-Nano"; > + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; Incorrect compatible. It's not cyclone5 board. cyclone5 is the SoC. There is no altr,socfpga This wasn't ever tested with bindings. > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + memory@0 { > + /* 1 GiB */ > + device_type = "memory"; > + reg = <0x0 0x40000000>; > + }; > + > + soc { > + fpga_axi: axi_h2f_lw_bridge@ff200000 { Follow DTS coding style. You just sent us something from downstream. > + compatible = "simple-bus"; > + reg = <0xff200000 0x00200000>; > + #address-cells = <1>; > + #size-cells = <1>; ranges would be after reg, but they are pointless here, no? Where is the child? > + ranges = <0x00000000 0xff200000 0x00200000>; > + }; > + }; > +}; > + > +&gmac1 { > + /* Uses a KSZ9031RNX phy */ > + status = "okay"; > + phy-mode = "rgmii"; > + > + rxd0-skew-ps = <420>; > + rxd1-skew-ps = <420>; > + rxd2-skew-ps = <420>; > + rxd3-skew-ps = <420>; > + txen-skew-ps = <0>; > + txc-skew-ps = <1860>; > + rxdv-skew-ps = <420>; > + rxc-skew-ps = <1680>; > +}; > + > +&gpio0 { > + status = "okay"; > +}; > + > +&gpio1 { > + status = "okay"; > +}; > + > +&gpio2 { > + status = "okay"; > +}; > + > +&i2c0 { > + clock-frequency = <100000>; > + status = "okay"; > + > + accelerometer@53 { > + compatible = "adi,adxl34x"; There is no such compatible and nothing in changelog refers to missing bindings. Always provide link in the changelog to your bindings which were not yet accepted. Best regards, Krzysztof
Hello Krzysztof, On Wed, Jan 29, 2025 at 10:27:22AM +0100, Krzysztof Kozlowski wrote: > On 28/01/2025 18:29, Uwe Kleine-König wrote: > > This dts is enough to make the board boot to Linux with the rootfs on > > a micro SD card. > > > > Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> > > --- > > diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dts > > new file mode 100644 > > index 000000000000..d1f23a57a94d > > --- /dev/null > > +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dts > > @@ -0,0 +1,90 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright (C) 2017, Intel Corporation > > + * > > + * based on socfpga_cyclone5_de0_nano_soc.dts > > + */ > > +/dts-v1/; > > + > > +#include "socfpga_cyclone5.dtsi" > > +#include <dt-bindings/interrupt-controller/irq.h> > > +#include <dt-bindings/gpio/gpio.h> > > + > > +/ { > > + model = "Terasic DE10-Nano"; > > + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; > > Incorrect compatible. It's not cyclone5 board. cyclone5 is the SoC. OK, adding "terasic,de10-nano". > There is no altr,socfpga What does that mean? `git grep \"altr,socfpga\" linus/master:arch/arm/boot` gives me 15 matches from other boards with socfpga SoCs. If you give me a bit more verbose description for the problem you're pointing out here, I can work on that. > This wasn't ever tested with bindings. I tried dt-validate -m -u Documentation/devicetree/bindings -p ~/work/kbuild/arm/Documentation/devicetree/bindings/processed-schema.json ~/work/kbuild/arm/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb which emitted a bunch of warnings and after processing some of them I gave up because they were all triggered by the soc.dtsi file. I started another try comparing the output for "my" socfpga_cyclone5_de10nano.dts with one for a file that only has the includes and the machine compatible. (Which generates 124 lines and 123 lines respectively.) I'll work on the diff between the two for the next revision. Or would you recommend a different approach? > > + chosen { > > + stdout-path = "serial0:115200n8"; > > + }; > > + > > + memory@0 { > > + /* 1 GiB */ > > + device_type = "memory"; > > + reg = <0x0 0x40000000>; > > + }; > > + > > + soc { > > + fpga_axi: axi_h2f_lw_bridge@ff200000 { > > Follow DTS coding style. You just sent us something from downstream. Indeed this is from downstream. Looking at the matching dt-validate output I guess just "axi@ff200000" would be appropriate?! > > + compatible = "simple-bus"; > > + reg = <0xff200000 0x00200000>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > ranges would be after reg, but they are pointless here, no? I thought it's "compatible", "reg" at the start, "status" at the end and the rest in-between in alphabetic order. What is the right ordering? > Where is the child? I intend to add children using dt-overlays. I have a prototype here, but that's still to embarrassing to show. > > + ranges = <0x00000000 0xff200000 0x00200000>; > > + }; > > + }; > > +}; > > + > > [...] > > +&i2c0 { > > + clock-frequency = <100000>; > > + status = "okay"; > > + > > + accelerometer@53 { > > + compatible = "adi,adxl34x"; > > There is no such compatible and nothing in changelog refers to missing > bindings. Always provide link in the changelog to your bindings which > were not yet accepted. Oops, indeed. Will make this "adi,adxl345" for the next revision. Best regards and thanks for your feedback, Uwe
On 29/01/2025 13:19, Uwe Kleine-König wrote: > Hello Krzysztof, > > On Wed, Jan 29, 2025 at 10:27:22AM +0100, Krzysztof Kozlowski wrote: >> On 28/01/2025 18:29, Uwe Kleine-König wrote: >>> This dts is enough to make the board boot to Linux with the rootfs on >>> a micro SD card. >>> >>> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> >>> --- >>> diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dts >>> new file mode 100644 >>> index 000000000000..d1f23a57a94d >>> --- /dev/null >>> +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dts >>> @@ -0,0 +1,90 @@ >>> +// SPDX-License-Identifier: GPL-2.0+ >>> +/* >>> + * Copyright (C) 2017, Intel Corporation >>> + * >>> + * based on socfpga_cyclone5_de0_nano_soc.dts >>> + */ >>> +/dts-v1/; >>> + >>> +#include "socfpga_cyclone5.dtsi" >>> +#include <dt-bindings/interrupt-controller/irq.h> >>> +#include <dt-bindings/gpio/gpio.h> >>> + >>> +/ { >>> + model = "Terasic DE10-Nano"; >>> + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; >> >> Incorrect compatible. It's not cyclone5 board. cyclone5 is the SoC. > > OK, adding "terasic,de10-nano". > >> There is no altr,socfpga > > What does that mean? > `git grep \"altr,socfpga\" linus/master:arch/arm/boot` gives me 15 > matches from other boards with socfpga SoCs. If you give me a bit more > verbose description for the problem you're pointing out here, I can work > on that. My bad, some poor git grep result. There is such compatible, so it is fine. > >> This wasn't ever tested with bindings. > > I tried > > dt-validate -m -u Documentation/devicetree/bindings -p ~/work/kbuild/arm/Documentation/devicetree/bindings/processed-schema.json ~/work/kbuild/arm/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb That's unusual way of running the check, but of course might work. > > which emitted a bunch of warnings and after processing some of them I > gave up because they were all triggered by the soc.dtsi file. I started These are fine, but you introduce issues purely here. > another try comparing the output for "my" socfpga_cyclone5_de10nano.dts > with one for a file that only has the includes and the machine > compatible. (Which generates 124 lines and 123 lines respectively.) > > I'll work on the diff between the two for the next revision. Or would > you recommend a different approach? > >>> + chosen { >>> + stdout-path = "serial0:115200n8"; >>> + }; >>> + >>> + memory@0 { >>> + /* 1 GiB */ >>> + device_type = "memory"; >>> + reg = <0x0 0x40000000>; >>> + }; >>> + >>> + soc { >>> + fpga_axi: axi_h2f_lw_bridge@ff200000 { >> >> Follow DTS coding style. You just sent us something from downstream. > > Indeed this is from downstream. Looking at the matching dt-validate > output I guess just "axi@ff200000" would be appropriate?! bus@ > >>> + compatible = "simple-bus"; >>> + reg = <0xff200000 0x00200000>; >>> + #address-cells = <1>; >>> + #size-cells = <1>; >> >> ranges would be after reg, but they are pointless here, no? > > I thought it's "compatible", "reg" at the start, "status" at the end and > the rest in-between in alphabetic order. What is the right ordering? DTS coding style could be clearer here. It exactly says what is the first, what is the second and what is the third. > >> Where is the child? > > I intend to add children using dt-overlays. I have a prototype here, but > that's still to embarrassing to show. The entire bus is in such case a bit confusing. If you have nothing connected here in the base board, does it really exist in FPGA bitstream? Best regards, Krzysztof
On Wed, Jan 29, 2025 at 09:35:21AM +0100, Uwe Kleine-König wrote: > Hello Andrew, > > On Tue, Jan 28, 2025 at 06:44:26PM +0100, Andrew Lunn wrote: > > > +&gmac1 { > > > + /* Uses a KSZ9031RNX phy */ > > > + status = "okay"; > > > + phy-mode = "rgmii"; > > > + > > > + rxd0-skew-ps = <420>; > > > + rxd1-skew-ps = <420>; > > > + rxd2-skew-ps = <420>; > > > + rxd3-skew-ps = <420>; > > > + txen-skew-ps = <0>; > > > + txc-skew-ps = <1860>; > > > + rxdv-skew-ps = <420>; > > > + rxc-skew-ps = <1680>; > > > +}; > > > > The convectional meaning of phy-mode 'rgmii' is that the PCB provides > > the 2ns delay. Here you are abusing the > > > > > + txc-skew-ps = <1860>; > > > + rxc-skew-ps = <1680>; > > > > To add these delays. > > Ah, at some point I already knew that. Thanks for repeating that hint. No problem a with the hint. This is a nice easy case. Some vendors have made a big mess with RGMII delays, hiding it in the bootloader, and giving customers bad advice. That is much harder to fix. > (Back then it was for > arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts.) > > > Please test without these two lines, and change phy-mode to > > 'rgmii-id'. 1680 is rather low, so it might not work. Look for CRC > > errors for received packets. > > I did an apt upgrade involving > 100 MB downloads with rgmii-id and > afterwards I had: > > # ip -stats link show dev eth0 > 2: eth0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAU > LT group default qlen 1000 > link/ether ee:5f:09:22:72:da brd ff:ff:ff:ff:ff:ff > RX: bytes packets errors dropped missed mcast > 158336739 113000 0 0 0 0 > TX: bytes packets errors dropped carrier collsns > 482481 5094 0 0 0 0 > > so that seems to be fine, right? Yes, this looks good. Thanks Andrew
On Tue, 28 Jan 2025 18:29:17 +0100, Uwe Kleine-König wrote: > This dts is enough to make the board boot to Linux with the rootfs on > a micro SD card. > > Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> > --- > Hello, > > in the variant I sent 15 min ago I fatfingered the address of the > linux-arm-kernel list. So here comes a resend with the right address ... > > Sorry for the noise > Uwe > > arch/arm/boot/dts/intel/socfpga/Makefile | 1 + > .../socfpga/socfpga_cyclone5_de10nano.dts | 90 +++++++++++++++++++ > 2 files changed, 91 insertions(+) > create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dts > My bot found new DTB warnings on the .dts files added or changed in this series. Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings are fixed by another series. Ultimately, it is up to the platform maintainer whether these warnings are acceptable or not. No need to reply unless the platform maintainer has comments. If you already ran DT checks and didn't see these error(s), then make sure dt-schema is up to date: pip3 install dtschema --upgrade New warnings running 'make CHECK_DTBS=y for arch/arm/boot/dts/intel/' for 20250128172917.4565-2-u.kleine-koenig@baylibre.com: arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /: compatible: 'oneOf' conditional failed, one must be fixed: ['altr,socfpga-cyclone5', 'altr,socfpga'] is too short 'altr,socfpga-cyclone5' is not one of ['altr,socfpga-arria5-socdk'] 'altr,socfpga-cyclone5' is not one of ['altr,socfpga-arria10-socdk'] 'altr,socfpga-cyclone5' is not one of ['enclustra,mercury-pe1', 'google,chameleon-v3'] 'altr,socfpga-cyclone5' is not one of ['altr,socfpga-cyclone5-socdk', 'denx,mcvevk', 'ebv,socrates', 'macnica,sodia', 'novtech,chameleon96', 'samtec,vining', 'terasic,de0-atlas', 'terasic,socfpga-cyclone5-sockit'] 'altr,socfpga-cyclone5' is not one of ['altr,socfpga-stratix10-socdk', 'altr,socfpga-stratix10-swvp'] 'altr,socfpga-vt' was expected 'altr,socfpga-arria5' was expected 'altr,socfpga-arria10' was expected 'enclustra,mercury-aa1' was expected 'altr,socfpga-cyclone5' was expected 'altr,socfpga-stratix10' was expected from schema $id: http://devicetree.org/schemas/arm/altera.yaml# arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: pmu@ff111000: 'reg' does not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/arm/pmu.yaml# arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: soc: stmmac-axi-config: 'ranges' is a required property from schema $id: http://devicetree.org/schemas/simple-bus.yaml# arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: soc: base_fpga_region: 'ranges' is a required property from schema $id: http://devicetree.org/schemas/simple-bus.yaml# arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: soc: sdramedac: 'ranges' is a required property from schema $id: http://devicetree.org/schemas/simple-bus.yaml# arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: soc: usbphy: 'ranges' is a required property from schema $id: http://devicetree.org/schemas/simple-bus.yaml# arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: amba: $nodename:0: 'amba' does not match '^([a-z][a-z0-9\-]+-bus|bus|localbus|soc|axi|ahb|apb)(@.+)?$' from schema $id: http://devicetree.org/schemas/simple-bus.yaml# arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: pdma@ffe01000: $nodename:0: 'pdma@ffe01000' does not match '^dma-controller(@.*)?$' from schema $id: http://devicetree.org/schemas/dma/arm,pl330.yaml# arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: base_fpga_region: $nodename:0: 'base_fpga_region' does not match '^fpga-region(@.*|-([0-9]|[1-9][0-9]+))?$' from schema $id: http://devicetree.org/schemas/fpga/fpga-region.yaml# arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: clkmgr@ffd04000: 'clocks' does not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml# arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: osc2: 'clock-frequency' is a required property from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml# arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: f2s_periph_ref_clk: 'clock-frequency' is a required property from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml# arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: f2s_sdram_ref_clk: 'clock-frequency' is a required property from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml# arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/main_pll@40: failed to match any schema with compatible: ['altr,socfpga-pll-clock'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/main_pll@40/mpuclk@48: failed to match any schema with compatible: ['altr,socfpga-perip-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/main_pll@40/mainclk@4c: failed to match any schema with compatible: ['altr,socfpga-perip-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/main_pll@40/dbg_base_clk@50: failed to match any schema with compatible: ['altr,socfpga-perip-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/main_pll@40/main_qspi_clk@54: failed to match any schema with compatible: ['altr,socfpga-perip-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/main_pll@40/main_nand_sdmmc_clk@58: failed to match any schema with compatible: ['altr,socfpga-perip-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/main_pll@40/cfg_h2f_usr0_clk@5c: failed to match any schema with compatible: ['altr,socfpga-perip-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/periph_pll@80: failed to match any schema with compatible: ['altr,socfpga-pll-clock'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/periph_pll@80/emac0_clk@88: failed to match any schema with compatible: ['altr,socfpga-perip-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/periph_pll@80/emac1_clk@8c: failed to match any schema with compatible: ['altr,socfpga-perip-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/periph_pll@80/per_qsi_clk@90: failed to match any schema with compatible: ['altr,socfpga-perip-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/periph_pll@80/per_nand_mmc_clk@94: failed to match any schema with compatible: ['altr,socfpga-perip-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/periph_pll@80/per_base_clk@98: failed to match any schema with compatible: ['altr,socfpga-perip-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/periph_pll@80/h2f_usr1_clk@9c: failed to match any schema with compatible: ['altr,socfpga-perip-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/sdram_pll@c0: failed to match any schema with compatible: ['altr,socfpga-pll-clock'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/sdram_pll@c0/ddr_dqs_clk@c8: failed to match any schema with compatible: ['altr,socfpga-perip-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/sdram_pll@c0/ddr_2x_dqs_clk@cc: failed to match any schema with compatible: ['altr,socfpga-perip-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/sdram_pll@c0/ddr_dq_clk@d0: failed to match any schema with compatible: ['altr,socfpga-perip-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/sdram_pll@c0/h2f_usr2_clk@d4: failed to match any schema with compatible: ['altr,socfpga-perip-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/mpu_periph_clk: failed to match any schema with compatible: ['altr,socfpga-perip-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/mpu_l2_ram_clk: failed to match any schema with compatible: ['altr,socfpga-perip-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/l4_main_clk: failed to match any schema with compatible: ['altr,socfpga-gate-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/l3_main_clk: failed to match any schema with compatible: ['altr,socfpga-perip-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/l3_mp_clk: failed to match any schema with compatible: ['altr,socfpga-gate-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/l3_sp_clk: failed to match any schema with compatible: ['altr,socfpga-gate-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/l4_mp_clk: failed to match any schema with compatible: ['altr,socfpga-gate-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/l4_sp_clk: failed to match any schema with compatible: ['altr,socfpga-gate-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/dbg_at_clk: failed to match any schema with compatible: ['altr,socfpga-gate-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/dbg_clk: failed to match any schema with compatible: ['altr,socfpga-gate-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/dbg_trace_clk: failed to match any schema with compatible: ['altr,socfpga-gate-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/dbg_timer_clk: failed to match any schema with compatible: ['altr,socfpga-gate-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/cfg_clk: failed to match any schema with compatible: ['altr,socfpga-gate-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/h2f_user0_clk: failed to match any schema with compatible: ['altr,socfpga-gate-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/emac_0_clk: failed to match any schema with compatible: ['altr,socfpga-gate-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/emac_1_clk: failed to match any schema with compatible: ['altr,socfpga-gate-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/usb_mp_clk: failed to match any schema with compatible: ['altr,socfpga-gate-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/spi_m_clk: failed to match any schema with compatible: ['altr,socfpga-gate-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/can0_clk: failed to match any schema with compatible: ['altr,socfpga-gate-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/can1_clk: failed to match any schema with compatible: ['altr,socfpga-gate-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/gpio_db_clk: failed to match any schema with compatible: ['altr,socfpga-gate-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/h2f_user1_clk: failed to match any schema with compatible: ['altr,socfpga-gate-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/sdmmc_clk: failed to match any schema with compatible: ['altr,socfpga-gate-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/sdmmc_clk_divided: failed to match any schema with compatible: ['altr,socfpga-gate-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/nand_x_clk: failed to match any schema with compatible: ['altr,socfpga-gate-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/nand_ecc_clk: failed to match any schema with compatible: ['altr,socfpga-gate-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/nand_clk: failed to match any schema with compatible: ['altr,socfpga-gate-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/qspi_clk: failed to match any schema with compatible: ['altr,socfpga-gate-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/ddr_dqs_clk_gate: failed to match any schema with compatible: ['altr,socfpga-gate-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/ddr_2x_dqs_clk_gate: failed to match any schema with compatible: ['altr,socfpga-gate-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/ddr_dq_clk_gate: failed to match any schema with compatible: ['altr,socfpga-gate-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/clkmgr@ffd04000/clocks/h2f_user2_clk: failed to match any schema with compatible: ['altr,socfpga-gate-clk'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: fpga_bridge@ff400000: $nodename:0: 'fpga_bridge@ff400000' does not match '^fpga-bridge(@.*|-([0-9]|[1-9][0-9]+))?$' from schema $id: http://devicetree.org/schemas/fpga/altr,socfpga-hps2fpga-bridge.yaml# arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: fpga_bridge@ff500000: $nodename:0: 'fpga_bridge@ff500000' does not match '^fpga-bridge(@.*|-([0-9]|[1-9][0-9]+))?$' from schema $id: http://devicetree.org/schemas/fpga/altr,socfpga-hps2fpga-bridge.yaml# arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/fpgamgr@ff706000: failed to match any schema with compatible: ['altr,socfpga-fpga-mgr'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/ethernet@ff700000: failed to match any schema with compatible: ['altr,socfpga-stmmac', 'snps,dwmac-3.70a', 'snps,dwmac'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/ethernet@ff702000: failed to match any schema with compatible: ['altr,socfpga-stmmac', 'snps,dwmac-3.70a', 'snps,dwmac'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/i2c@ffc04000/accelerometer@53: failed to match any schema with compatible: ['adi,adxl34x'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/eccmgr: failed to match any schema with compatible: ['altr,socfpga-ecc-manager'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/eccmgr/l2-ecc@ffd08140: failed to match any schema with compatible: ['altr,socfpga-l2-ecc'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/eccmgr/ocram-ecc@ffd08144: failed to match any schema with compatible: ['altr,socfpga-ocram-ecc'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: sram@ffff0000: '#address-cells' is a required property from schema $id: http://devicetree.org/schemas/sram/sram.yaml# arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: sram@ffff0000: '#size-cells' is a required property from schema $id: http://devicetree.org/schemas/sram/sram.yaml# arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: sram@ffff0000: 'ranges' is a required property from schema $id: http://devicetree.org/schemas/sram/sram.yaml# arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: spi@ff705000: resets: [[6, 37]] is too short from schema $id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml# arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: /soc/sdramedac: failed to match any schema with compatible: ['altr,sdram-edac'] arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: sysmgr@ffd08000: compatible: 'oneOf' conditional failed, one must be fixed: ['altr,sys-mgr', 'syscon'] is too long 'altr,sys-mgr-s10' was expected 'altr,sys-mgr' was expected from schema $id: http://devicetree.org/schemas/soc/altera/altr,sys-mgr.yaml# arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: timer0@ffc08000: 'reset-names' does not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/timer/snps,dw-apb-timer.yaml# arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: timer1@ffc09000: 'reset-names' does not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/timer/snps,dw-apb-timer.yaml# arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: timer2@ffd00000: 'reset-names' does not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/timer/snps,dw-apb-timer.yaml# arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: timer3@ffd01000: 'reset-names' does not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/timer/snps,dw-apb-timer.yaml# arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: axi_h2f_lw_bridge@ff200000: $nodename:0: 'axi_h2f_lw_bridge@ff200000' does not match '^([a-z][a-z0-9\-]+-bus|bus|localbus|soc|axi|ahb|apb)(@.+)?$' from schema $id: http://devicetree.org/schemas/simple-bus.yaml#
Hello, On Wed, Jan 29, 2025 at 01:34:28PM +0100, Krzysztof Kozlowski wrote: > On 29/01/2025 13:19, Uwe Kleine-König wrote: > > On Wed, Jan 29, 2025 at 10:27:22AM +0100, Krzysztof Kozlowski wrote: > >> On 28/01/2025 18:29, Uwe Kleine-König wrote: > > I tried > > > > dt-validate -m -u Documentation/devicetree/bindings -p ~/work/kbuild/arm/Documentation/devicetree/bindings/processed-schema.json ~/work/kbuild/arm/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb > > That's unusual way of running the check, but of course might work. This is what `make` does when running one of the dt check targets. I didn't find a way to call this via make for just a single dtb. > >>> + soc { > >>> + fpga_axi: axi_h2f_lw_bridge@ff200000 { > >> > >> Follow DTS coding style. You just sent us something from downstream. > > > > Indeed this is from downstream. Looking at the matching dt-validate > > output I guess just "axi@ff200000" would be appropriate?! > > bus@ ok. > >>> + compatible = "simple-bus"; > >>> + reg = <0xff200000 0x00200000>; > >>> + #address-cells = <1>; > >>> + #size-cells = <1>; > >> > >> ranges would be after reg, but they are pointless here, no? > > > > I thought it's "compatible", "reg" at the start, "status" at the end and > > the rest in-between in alphabetic order. What is the right ordering? > > DTS coding style could be clearer here. It exactly says what is the > first, what is the second and what is the third. I found Documentation/devicetree/bindings/dts-coding-style.rst now. > >> Where is the child? > > > > I intend to add children using dt-overlays. I have a prototype here, but > > that's still to embarrassing to show. > > The entire bus is in such case a bit confusing. If you have nothing > connected here in the base board, does it really exist in FPGA bitstream? I'm unsure. If I don't load an FPGA image, the machine boots fine but IIRC accessing the address space results in an error. If I load an FPGA image, its register space appears at that address. So technically it might be ok to drop the node, but from a practical POV it's useful to have it in the board.dtb to not have to create that note in each overlay. If that is good enough for you, I'll go with a comment in that node that tells about the expectation that it will be filled using an overlay. Best regards Uwe
diff --git a/arch/arm/boot/dts/intel/socfpga/Makefile b/arch/arm/boot/dts/intel/socfpga/Makefile index c467828aeb4b..7f69a0355ea5 100644 --- a/arch/arm/boot/dts/intel/socfpga/Makefile +++ b/arch/arm/boot/dts/intel/socfpga/Makefile @@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \ socfpga_cyclone5_mcvevk.dtb \ socfpga_cyclone5_socdk.dtb \ socfpga_cyclone5_de0_nano_soc.dtb \ + socfpga_cyclone5_de10nano.dtb \ socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_socrates.dtb \ socfpga_cyclone5_sodia.dtb \ diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dts new file mode 100644 index 000000000000..d1f23a57a94d --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dts @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017, Intel Corporation + * + * based on socfpga_cyclone5_de0_nano_soc.dts + */ +/dts-v1/; + +#include "socfpga_cyclone5.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Terasic DE10-Nano"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + /* 1 GiB */ + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + soc { + fpga_axi: axi_h2f_lw_bridge@ff200000 { + compatible = "simple-bus"; + reg = <0xff200000 0x00200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0xff200000 0x00200000>; + }; + }; +}; + +&gmac1 { + /* Uses a KSZ9031RNX phy */ + status = "okay"; + phy-mode = "rgmii"; + + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + txen-skew-ps = <0>; + txc-skew-ps = <1860>; + rxdv-skew-ps = <420>; + rxc-skew-ps = <1680>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; + + accelerometer@53 { + compatible = "adi,adxl34x"; + reg = <0x53>; + /* HPS_GSENSOR_INT is routed to UART0_RX/CAN0_RX/SPIM0_SS1/HPS_GPIO61 */ + interrupt-parent = <&portc>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&mmc0 { + /* micro SD card socket J11 */ + status = "okay"; +}; + +&uart0 { + /* + * Accessible via USB (FT232R) on Mini-USB plug J4 + * RX = TRACE_D0/SPIS0_CLK/UART0_RX/HPS_GPIO49 + * TX = TRACE_D1/SPIS0_MOSI/UART0_TX/HPS_GPIO50 + */ + clock-frequency = <100000000>; +};
This dts is enough to make the board boot to Linux with the rootfs on a micro SD card. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> --- Hello, in the variant I sent 15 min ago I fatfingered the address of the linux-arm-kernel list. So here comes a resend with the right address ... Sorry for the noise Uwe arch/arm/boot/dts/intel/socfpga/Makefile | 1 + .../socfpga/socfpga_cyclone5_de10nano.dts | 90 +++++++++++++++++++ 2 files changed, 91 insertions(+) create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dts base-commit: 5ffa57f6eecefababb8cbe327222ef171943b183