| Message ID | 20250125-topic-x1p4_dts-v1-0-02659a08b044@oss.qualcomm.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | X1P42100 DT and PCIe PHY bits | expand |
On 25.01.25 04:31, Konrad Dybcio wrote: > X1P42100 is a(n indirect) derivative of X1E80100 - the silicon is > actually different and it's not a fused down part. > > Introduce the DTS bits required to support it by mostly reusing the > X1E SoC and CRD DTSIs. The most notable differences from our software > PoV are a different GPU (support for which will be added later), 4 > less CPUs and some nuances in the PCIe hardware. > > This series very strictly depends on the NOCSR PCIe PHY reset patches. > > Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> > --- > Konrad Dybcio (6): > dt-bindings: phy: qcom,qmp-pcie: Add X1P42100 PCIe Gen4x4 PHY > dt-bindings: phy: qcom,qmp-pcie: Drop reset number constraints > phy: qcom: qmp-pcie: Add X1P42100 Gen4x4 PHY > arm64: dts: qcom: x1e80100: Wire up PCIe PHY NOCSR resets > arm64: dts: qcom: Commonize X1 CRD DTSI > arm64: dts: qcom: Add X1P42100 SoC and CRD > > .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 26 +- > arch/arm64/boot/dts/qcom/Makefile | 1 + > .../dts/qcom/{x1e80100-crd.dts => x1-crd.dtsi} | 7 - > arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 1270 +------------------- > arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi | 2 +- > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 44 +- > arch/arm64/boot/dts/qcom/x1p42100-crd.dts | 17 + > arch/arm64/boot/dts/qcom/x1p42100.dtsi | 81 ++ > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 18 + > 9 files changed, 148 insertions(+), 1318 deletions(-) > --- > base-commit: d7dfdec72fb32629d1affc32ff37a66a7fd1fb53 > change-id: 20250125-topic-x1p4_dts-3b9509bce3a3 > prerequisite-message-id: 20250121094140.4006801-1-quic_wenbyao@quicinc.com > prerequisite-patch-id: 719a1c1319a8f25be57f1e9bc68887684ff0d7cd > prerequisite-patch-id: 44ff71b8033fc91867a83a2f8f063fd0d9951d5e > > Best regards, Hi Konrad, I applied the series, and its successfully tested on Lenovo Thinkbook 16 G7 QOY. [1] Thank you! [1] https://github.com/jglathe/linux_ms_dev_kit/commits/jg/ubuntu-qcom-x1e-6.13/ Tested-by: Jens Glathe <jens.glathe@oldschoolsolutions.biz> with best regards Jens
X1P42100 is a(n indirect) derivative of X1E80100 - the silicon is actually different and it's not a fused down part. Introduce the DTS bits required to support it by mostly reusing the X1E SoC and CRD DTSIs. The most notable differences from our software PoV are a different GPU (support for which will be added later), 4 less CPUs and some nuances in the PCIe hardware. This series very strictly depends on the NOCSR PCIe PHY reset patches. Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> --- Konrad Dybcio (6): dt-bindings: phy: qcom,qmp-pcie: Add X1P42100 PCIe Gen4x4 PHY dt-bindings: phy: qcom,qmp-pcie: Drop reset number constraints phy: qcom: qmp-pcie: Add X1P42100 Gen4x4 PHY arm64: dts: qcom: x1e80100: Wire up PCIe PHY NOCSR resets arm64: dts: qcom: Commonize X1 CRD DTSI arm64: dts: qcom: Add X1P42100 SoC and CRD .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 26 +- arch/arm64/boot/dts/qcom/Makefile | 1 + .../dts/qcom/{x1e80100-crd.dts => x1-crd.dtsi} | 7 - arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 1270 +------------------- arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi | 2 +- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 44 +- arch/arm64/boot/dts/qcom/x1p42100-crd.dts | 17 + arch/arm64/boot/dts/qcom/x1p42100.dtsi | 81 ++ drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 18 + 9 files changed, 148 insertions(+), 1318 deletions(-) --- base-commit: d7dfdec72fb32629d1affc32ff37a66a7fd1fb53 change-id: 20250125-topic-x1p4_dts-3b9509bce3a3 prerequisite-message-id: 20250121094140.4006801-1-quic_wenbyao@quicinc.com prerequisite-patch-id: 719a1c1319a8f25be57f1e9bc68887684ff0d7cd prerequisite-patch-id: 44ff71b8033fc91867a83a2f8f063fd0d9951d5e Best regards,