| Message ID | 173699827608.29706.6576459159016491419-0@git.sr.ht (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [qemu] target/riscv: Check ext_zca for misaligned return address of mret/sret. | expand |
On Thu, Jan 16, 2025 at 1:32 PM ~yuming <yuming@git.sr.ht> wrote: > > From: Yu-Ming Chang <yumin686@andestech.com> > > Only check misa.C will cause issues when ext_zca is enabled without > misa.C being set. For example, only enable ext_zce. Thanks for the patch! I'm not clear what the problem is and what this commit fixes. Do you mind updating this to clearly describe what you are fixing? > > Signed-off-by: Yu-Ming Chang <yumin686@andestech.com> > --- > target/riscv/op_helper.c | 12 ++++++++---- > 1 file changed, 8 insertions(+), 4 deletions(-) > > diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c > index eddedacf4b..891002f954 100644 > --- a/target/riscv/op_helper.c > +++ b/target/riscv/op_helper.c > @@ -269,8 +269,10 @@ target_ulong helper_sret(CPURISCVState *env) > } > > target_ulong retpc = env->sepc; > - if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) { > - riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); > + if (!riscv_has_ext(env, RVC) && !env_archcpu(env)->cfg.ext_zca) { I think you can just check ext_zca, as misa.C enables ext_zca Alistair > + if ((retpc & 0x3) != 0) { > + riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); > + } > } > > if (get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) { > @@ -328,8 +330,10 @@ target_ulong helper_mret(CPURISCVState *env) > } > > target_ulong retpc = env->mepc; > - if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) { > - riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); > + if (!riscv_has_ext(env, RVC) && !env_archcpu(env)->cfg.ext_zca) { > + if ((retpc & 0x3) != 0) { > + riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); > + } > } > > uint64_t mstatus = env->mstatus; > -- > 2.45.2 >
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index eddedacf4b..891002f954 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -269,8 +269,10 @@ target_ulong helper_sret(CPURISCVState *env) } target_ulong retpc = env->sepc; - if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) { - riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); + if (!riscv_has_ext(env, RVC) && !env_archcpu(env)->cfg.ext_zca) { + if ((retpc & 0x3) != 0) { + riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); + } } if (get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) { @@ -328,8 +330,10 @@ target_ulong helper_mret(CPURISCVState *env) } target_ulong retpc = env->mepc; - if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) { - riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); + if (!riscv_has_ext(env, RVC) && !env_archcpu(env)->cfg.ext_zca) { + if ((retpc & 0x3) != 0) { + riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); + } } uint64_t mstatus = env->mstatus;