| Message ID | 20250206083655.3005151-2-grzegorz.nitka@intel.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | E825C PTP cleanup | expand |
| Context | Check | Description |
|---|---|---|
| netdev/tree_selection | success | Guessing tree name failed - patch did not apply |
On Thu, Feb 06, 2025 at 09:36:53AM +0100, Grzegorz Nitka wrote: > From: Karol Kolacinski <karol.kolacinski@intel.com> > > Implement setting GLTSYN_SYNC_DLAY for E825C products. > This is the execution delay compensation of SYNC command between > PHC and PHY. > Also, refactor the code by changing ice_ptp_init_phc_eth56g function > name to ice_ptp_init_phc_e825, to be consistent with the naming pattern > for other devices. Adding support for GLTSYN_SYNC_DLAY and the refactor seem to be two distinct changes, albeit touching common code. I think it would be slightly better to split this into two patches. > Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com> > Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com> > Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com> ...
> -----Original Message----- > From: Simon Horman <horms@kernel.org> > Sent: Friday, February 7, 2025 11:04 AM > To: Nitka, Grzegorz <grzegorz.nitka@intel.com> > Cc: intel-wired-lan@lists.osuosl.org; netdev@vger.kernel.org; Nguyen, > Anthony L <anthony.l.nguyen@intel.com>; Kitszel, Przemyslaw > <przemyslaw.kitszel@intel.com>; Kolacinski, Karol > <karol.kolacinski@intel.com> > Subject: Re: [PATCH iwl-next v1 1/3] ice: Add sync delay for E825C > > On Thu, Feb 06, 2025 at 09:36:53AM +0100, Grzegorz Nitka wrote: > > From: Karol Kolacinski <karol.kolacinski@intel.com> > > > > Implement setting GLTSYN_SYNC_DLAY for E825C products. > > This is the execution delay compensation of SYNC command between > > PHC and PHY. > > Also, refactor the code by changing ice_ptp_init_phc_eth56g function > > name to ice_ptp_init_phc_e825, to be consistent with the naming pattern > > for other devices. > > Adding support for GLTSYN_SYNC_DLAY and the refactor seem > to be two distinct changes, albeit touching common code. > > I think it would be slightly better to split this into two patches. > Sure, will exclude this commit from the series and will submit it as separate patch. Thanks for your review and valuable feedback. > > Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com> > > Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com> > > Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com> > > ...
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c index 3e824f7b30c0..c3dea6d61de4 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c @@ -2650,18 +2650,18 @@ static void ice_sb_access_ena_eth56g(struct ice_hw *hw, bool enable) } /** - * ice_ptp_init_phc_eth56g - Perform E82X specific PHC initialization + * ice_ptp_init_phc_e825 - Perform E825 specific PHC initialization * @hw: pointer to HW struct * - * Perform PHC initialization steps specific to E82X devices. + * Perform E825-specific PTP hardware clock initialization steps. * - * Return: - * * %0 - success - * * %other - failed to initialize CGU + * Return: 0 on success, negative error code otherwise. */ -static int ice_ptp_init_phc_eth56g(struct ice_hw *hw) +static int ice_ptp_init_phc_e825(struct ice_hw *hw) { ice_sb_access_ena_eth56g(hw, true); + ice_ptp_cfg_sync_delay(hw, ICE_E825_SYNC_DELAY); + /* Initialize the Clock Generation Unit */ return ice_init_cgu_e82x(hw); } @@ -6123,7 +6123,7 @@ int ice_ptp_init_phc(struct ice_hw *hw) case ICE_MAC_GENERIC: return ice_ptp_init_phc_e82x(hw); case ICE_MAC_GENERIC_3K_E825: - return ice_ptp_init_phc_eth56g(hw); + return ice_ptp_init_phc_e825(hw); default: return -EOPNOTSUPP; } diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h index 8442d1d60351..10295fa9a383 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h @@ -324,7 +324,10 @@ extern const struct ice_vernier_info_e82x e822_vernier[NUM_ICE_PTP_LNK_SPD]; */ #define ICE_E810_PLL_FREQ 812500000 #define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL + +/* PHC to PHY synchronization delay definitions */ #define ICE_E810_E830_SYNC_DELAY 0 +#define ICE_E825_SYNC_DELAY 6 /* Device agnostic functions */ u8 ice_get_ptp_src_clock_index(struct ice_hw *hw);