| Message ID | 20250206121341.118337-5-corvin.koehne@gmail.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | vfio/igd: sync PCI IDs with i915 | expand |
On 2/6/25 20:13, Corvin Köhne wrote: > From: Corvin Köhne <c.koehne@beckhoff.com> > > We're currently missing some GPU IDs already supported by the i915 > kernel driver. Additionally, we've treated IvyBridge as gen 6 in the > past. According to i915 it's gen 7 [1]. It shouldn't cause any issues > yet because we treat gen 6 and gen 7 the same way. Nevertheless, we > should use the correct generation to avoid any confusion. > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/i915/i915_pci.c?h=v6.13#n330 > > Signed-off-by: Corvin Köhne <c.koehne@beckhoff.com> > --- > hw/vfio/igd.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/hw/vfio/igd.c b/hw/vfio/igd.c > index e5d7006ce2..7bbf018efc 100644 > --- a/hw/vfio/igd.c > +++ b/hw/vfio/igd.c > @@ -64,7 +64,7 @@ struct igd_device { > > static const struct igd_device igd_devices[] = { > INTEL_SNB_IDS(IGD_DEVICE, 6), > - INTEL_IVB_IDS(IGD_DEVICE, 6), > + INTEL_IVB_IDS(IGD_DEVICE, 7), > INTEL_HSW_IDS(IGD_DEVICE, 7), > INTEL_VLV_IDS(IGD_DEVICE, 7), > INTEL_BDW_IDS(IGD_DEVICE, 8), > @@ -73,8 +73,10 @@ static const struct igd_device igd_devices[] = { > INTEL_BXT_IDS(IGD_DEVICE, 9), > INTEL_KBL_IDS(IGD_DEVICE, 9), > INTEL_CFL_IDS(IGD_DEVICE, 9), > + INTEL_WHL_IDS(IGD_DEVICE, 9), > INTEL_CML_IDS(IGD_DEVICE, 9), > INTEL_GLK_IDS(IGD_DEVICE, 9), > + INTEL_CNL_IDS(IGD_DEVICE, 9), > INTEL_ICL_IDS(IGD_DEVICE, 11), > INTEL_EHL_IDS(IGD_DEVICE, 11), > INTEL_JSL_IDS(IGD_DEVICE, 11), > @@ -86,6 +88,8 @@ static const struct igd_device igd_devices[] = { > INTEL_RPLS_IDS(IGD_DEVICE, 12), > INTEL_RPLU_IDS(IGD_DEVICE, 12), > INTEL_RPLP_IDS(IGD_DEVICE, 12), > + INTEL_ARL_IDS(IGD_DEVICE, 12), > + INTEL_MTL_IDS(IGD_DEVICE, 12), According to i915 driver [1], DSM becomes a part of BAR 2 in MTL/ARL. All accesses to DSM from CPU should be via BAR I think. BARs are mapped in guest address space to host address space by QEMU when passthrough, as a common behavior, just like normal discrete GPUs. Though IGD takes a memory region as DSM, it should be reserved by firmware and not directly accessible by host also, like GTT memory, since arch/x86/kernel/early-quirks.c no longer reserves DSM for MTL/ ARL. Appling the BDSM quirk would bring issues to MTL/ARL. Probably there is no special workarounds needed for MTL and later IGD devices. But intel hasn't made the MTL/ARL/LNL datasheet publicly available yet, I can not confirm it :( If Intel really decided to not using BDSM on MTL+, we can just have a fixed id list for igd devices. [1] https://github.com/torvalds/linux/blob/69b8923f5003664e3ffef102e73333edfa2abdcf/drivers/gpu/drm/i915/gem/i915_gem_stolen.c#L918 > }; > > /*
diff --git a/hw/vfio/igd.c b/hw/vfio/igd.c index e5d7006ce2..7bbf018efc 100644 --- a/hw/vfio/igd.c +++ b/hw/vfio/igd.c @@ -64,7 +64,7 @@ struct igd_device { static const struct igd_device igd_devices[] = { INTEL_SNB_IDS(IGD_DEVICE, 6), - INTEL_IVB_IDS(IGD_DEVICE, 6), + INTEL_IVB_IDS(IGD_DEVICE, 7), INTEL_HSW_IDS(IGD_DEVICE, 7), INTEL_VLV_IDS(IGD_DEVICE, 7), INTEL_BDW_IDS(IGD_DEVICE, 8), @@ -73,8 +73,10 @@ static const struct igd_device igd_devices[] = { INTEL_BXT_IDS(IGD_DEVICE, 9), INTEL_KBL_IDS(IGD_DEVICE, 9), INTEL_CFL_IDS(IGD_DEVICE, 9), + INTEL_WHL_IDS(IGD_DEVICE, 9), INTEL_CML_IDS(IGD_DEVICE, 9), INTEL_GLK_IDS(IGD_DEVICE, 9), + INTEL_CNL_IDS(IGD_DEVICE, 9), INTEL_ICL_IDS(IGD_DEVICE, 11), INTEL_EHL_IDS(IGD_DEVICE, 11), INTEL_JSL_IDS(IGD_DEVICE, 11), @@ -86,6 +88,8 @@ static const struct igd_device igd_devices[] = { INTEL_RPLS_IDS(IGD_DEVICE, 12), INTEL_RPLU_IDS(IGD_DEVICE, 12), INTEL_RPLP_IDS(IGD_DEVICE, 12), + INTEL_ARL_IDS(IGD_DEVICE, 12), + INTEL_MTL_IDS(IGD_DEVICE, 12), }; /*