Message ID | 20250206085034.1978172-6-sumang@marvell.com (mailing list archive) |
---|---|
State | Superseded |
Delegated to: | Netdev Maintainers |
Headers | show |
Series | Add af_xdp support for cn10k | expand |
On Thu, Feb 06, 2025 at 02:20:33PM +0530, Suman Ghosh wrote: > Implement necessary APIs required for AF_XDP transmit. > > Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> > Signed-off-by: Suman Ghosh <sumang@marvell.com> ... > diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c > index 44137160bdf6..b012d8794f18 100644 > --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c > +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c > @@ -22,6 +22,12 @@ > #include "cn10k.h" > > #define CQE_ADDR(CQ, idx) ((CQ)->cqe_base + ((CQ)->cqe_size * (idx))) > +#define READ_FREE_SQE(SQ, free_sqe) \ > + do { \ > + typeof(SQ) _SQ = (SQ); \ > + free_sqe = (((_SQ)->cons_head - (_SQ)->head - 1 + (_SQ)->sqe_cnt) \ > + & ((_SQ)->sqe_cnt - 1)); \ > + } while (0) It looks like READ_FREE_SQE() could be a function rather than a macro. And, as an aside, CQE_ADDR could be too. > #define PTP_PORT 0x13F > /* PTPv2 header Original Timestamp starts at byte offset 34 and > * contains 6 byte seconds field and 4 byte nano seconds field. ...
>> diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c >> b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c >> index 44137160bdf6..b012d8794f18 100644 >> --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c >> +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c >> @@ -22,6 +22,12 @@ >> #include "cn10k.h" >> >> #define CQE_ADDR(CQ, idx) ((CQ)->cqe_base + ((CQ)->cqe_size * (idx))) >> +#define READ_FREE_SQE(SQ, free_sqe) \ >> + do { \ >> + typeof(SQ) _SQ = (SQ); \ >> + free_sqe = (((_SQ)->cons_head - (_SQ)->head - 1 + (_SQ)- >>sqe_cnt) \ >> + & ((_SQ)->sqe_cnt - 1)); >\ >> + } while (0) > >It looks like READ_FREE_SQE() could be a function rather than a macro. >And, as an aside, CQE_ADDR could be too. [Suman] I will address the READ_FREE_SQE, but CQE_ADDR will push a separate patch in net tree. > >> #define PTP_PORT 0x13F >> /* PTPv2 header Original Timestamp starts at byte offset 34 and >> * contains 6 byte seconds field and 4 byte nano seconds field. > >...
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h index 60508971b62f..19e9e2e72233 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h @@ -1181,4 +1181,5 @@ static inline int mcam_entry_cmp(const void *a, const void *b) dma_addr_t otx2_dma_map_skb_frag(struct otx2_nic *pfvf, struct sk_buff *skb, int seg, int *len); void otx2_dma_unmap_skb_frags(struct otx2_nic *pfvf, struct sg_list *sg); +int otx2_read_free_sqe(struct otx2_nic *pfvf, u16 qidx); #endif /* OTX2_COMMON_H */ diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c index 44137160bdf6..b012d8794f18 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c @@ -22,6 +22,12 @@ #include "cn10k.h" #define CQE_ADDR(CQ, idx) ((CQ)->cqe_base + ((CQ)->cqe_size * (idx))) +#define READ_FREE_SQE(SQ, free_sqe) \ + do { \ + typeof(SQ) _SQ = (SQ); \ + free_sqe = (((_SQ)->cons_head - (_SQ)->head - 1 + (_SQ)->sqe_cnt) \ + & ((_SQ)->sqe_cnt - 1)); \ + } while (0) #define PTP_PORT 0x13F /* PTPv2 header Original Timestamp starts at byte offset 34 and * contains 6 byte seconds field and 4 byte nano seconds field. @@ -1163,7 +1169,7 @@ bool otx2_sq_append_skb(void *dev, struct netdev_queue *txq, /* Check if there is enough room between producer * and consumer index. */ - free_desc = (sq->cons_head - sq->head - 1 + sq->sqe_cnt) & (sq->sqe_cnt - 1); + READ_FREE_SQE(sq, free_desc); if (free_desc < sq->sqe_thresh) return false; @@ -1402,6 +1408,21 @@ static void otx2_xdp_sqe_add_sg(struct otx2_snd_queue *sq, sq->sg[sq->head].skb = (u64)xdpf; } +int otx2_read_free_sqe(struct otx2_nic *pfvf, u16 qidx) +{ + struct otx2_snd_queue *sq; + int free_sqe; + + sq = &pfvf->qset.sq[qidx]; + READ_FREE_SQE(sq, free_sqe); + if (free_sqe < sq->sqe_thresh) { + netdev_warn(pfvf->netdev, "No free sqe for Send queue%d\n", qidx); + return 0; + } + + return free_sqe - sq->sqe_thresh; +} + bool otx2_xdp_sq_append_pkt(struct otx2_nic *pfvf, struct xdp_frame *xdpf, u64 iova, int len, u16 qidx, u16 flags) { @@ -1410,7 +1431,7 @@ bool otx2_xdp_sq_append_pkt(struct otx2_nic *pfvf, struct xdp_frame *xdpf, int offset, free_sqe; sq = &pfvf->qset.sq[qidx]; - free_sqe = (sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb; + READ_FREE_SQE(sq, free_sqe); if (free_sqe < sq->sqe_thresh) return false;