| Message ID | 20250224063046.1438006-2-sai.krishna.musham@amd.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add support for PCIe RP PERST# | expand |
On Mon, Feb 24, 2025 at 12:00:45PM +0530, Sai Krishna Musham wrote: > Introduce `reset-gpios` property to enable GPIO-based control of > the PCIe RP PERST# signal, generating assert and deassert signals. > > Signed-off-by: Sai Krishna Musham <sai.krishna.musham@amd.com> > --- > This patch depends on the following patch series. > https://lore.kernel.org/all/20250217072713.635643-2-thippeswamy.havalige@amd.com/ > --- > .../devicetree/bindings/pci/xilinx-versal-cpm.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > index b63a759ec2d7..293ed36d0cea 100644 > --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > @@ -33,6 +33,9 @@ properties: > - const: cpm_csr > minItems: 2 > > + reset-gpios: > + description: GPIO used as PERST# signal. Please refer to pci.txt. > + > interrupts: > maxItems: 1 > > @@ -63,6 +66,7 @@ properties: > required: > - reg > - reg-names > + - reset-gpios This is an ABI break. If you make it required now, old DTS will be broken. > - "#interrupt-cells" > - interrupts > - interrupt-map > @@ -99,6 +103,7 @@ examples: > reg = <0x0 0xfca10000 0x0 0x1000>, > <0x6 0x00000000 0x0 0x10000000>; > reg-names = "cpm_slcr", "cfg"; > + reset-gpios = <&gpio1 38 0x01>; Please use proper defines in include/dt-bindings/gpio/gpio.h for the GPIO polarity. > pcie_intc_0: interrupt-controller { > #address-cells = <0>; > #interrupt-cells = <1>; > @@ -127,6 +132,7 @@ examples: > <0x06 0x00000000 0x00 0x1000000>, > <0x00 0xfce20000 0x00 0x1000000>; > reg-names = "cpm_slcr", "cfg", "cpm_csr"; > + reset-gpios = <&gpio1 38 0x01>; Same here. - Mani
diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml index b63a759ec2d7..293ed36d0cea 100644 --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml @@ -33,6 +33,9 @@ properties: - const: cpm_csr minItems: 2 + reset-gpios: + description: GPIO used as PERST# signal. Please refer to pci.txt. + interrupts: maxItems: 1 @@ -63,6 +66,7 @@ properties: required: - reg - reg-names + - reset-gpios - "#interrupt-cells" - interrupts - interrupt-map @@ -99,6 +103,7 @@ examples: reg = <0x0 0xfca10000 0x0 0x1000>, <0x6 0x00000000 0x0 0x10000000>; reg-names = "cpm_slcr", "cfg"; + reset-gpios = <&gpio1 38 0x01>; pcie_intc_0: interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; @@ -127,6 +132,7 @@ examples: <0x06 0x00000000 0x00 0x1000000>, <0x00 0xfce20000 0x00 0x1000000>; reg-names = "cpm_slcr", "cfg", "cpm_csr"; + reset-gpios = <&gpio1 38 0x01>; pcie_intc_1: interrupt-controller { #address-cells = <0>;
Introduce `reset-gpios` property to enable GPIO-based control of the PCIe RP PERST# signal, generating assert and deassert signals. Signed-off-by: Sai Krishna Musham <sai.krishna.musham@amd.com> --- This patch depends on the following patch series. https://lore.kernel.org/all/20250217072713.635643-2-thippeswamy.havalige@amd.com/ --- .../devicetree/bindings/pci/xilinx-versal-cpm.yaml | 6 ++++++ 1 file changed, 6 insertions(+)