| Message ID | 20250223122227.725233-8-ivo.ivanov.ivanov1@gmail.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | phy: samsung: add Exynos2200 SNPS eUSB2 driver | expand |
On Sun, Feb 23, 2025 at 02:22:26PM +0200, Ivaylo Ivanov wrote: > The Exynos2200 SoC reuses the Synopsis eUSB2 PHY IP, alongside an > external repeater, for USB 2.0. Add support for it to the existing > driver. > > Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> > --- > drivers/phy/Kconfig | 2 +- > drivers/phy/phy-snps-eusb2.c | 172 +++++++++++++++++++++++++++++++++++ > 2 files changed, 173 insertions(+), 1 deletion(-) > > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig > index 11c166204..58c911e1b 100644 > --- a/drivers/phy/Kconfig > +++ b/drivers/phy/Kconfig > @@ -45,7 +45,7 @@ config PHY_PISTACHIO_USB > > config PHY_SNPS_EUSB2 > tristate "SNPS eUSB2 PHY Driver" > - depends on OF && (ARCH_QCOM || COMPILE_TEST) > + depends on OF && (ARCH_EXYNOS || ARCH_QCOM || COMPILE_TEST) > select GENERIC_PHY > help > Enable support for the USB high-speed SNPS eUSB2 phy on select > diff --git a/drivers/phy/phy-snps-eusb2.c b/drivers/phy/phy-snps-eusb2.c > index 7a242fe32..67a19d671 100644 > --- a/drivers/phy/phy-snps-eusb2.c > +++ b/drivers/phy/phy-snps-eusb2.c > @@ -13,6 +13,39 @@ > #include <linux/regulator/consumer.h> > #include <linux/reset.h> > > +#define EXYNOS_USB_PHY_HS_PHY_CTRL_RST (0x0) > +#define USB_PHY_RST_MASK GENMASK(1, 0) > +#define UTMI_PORT_RST_MASK GENMASK(5, 4) > + > +#define EXYNOS_USB_PHY_HS_PHY_CTRL_COMMON (0x4) > +#define RPTR_MODE BIT(10) > +#define FSEL_20_MHZ_VAL (0x1) > +#define FSEL_24_MHZ_VAL (0x2) > +#define FSEL_26_MHZ_VAL (0x3) > +#define FSEL_48_MHZ_VAL (0x2) > + > +#define EXYNOS_USB_PHY_CFG_PLLCFG0 (0x8) > +#define PHY_CFG_PLL_FB_DIV_19_8_MASK GENMASK(19, 8) > +#define DIV_19_8_19_2_MHZ_VAL (0x170) > +#define DIV_19_8_20_MHZ_VAL (0x160) > +#define DIV_19_8_24_MHZ_VAL (0x120) > +#define DIV_19_8_26_MHZ_VAL (0x107) > +#define DIV_19_8_48_MHZ_VAL (0x120) > + > +#define EXYNOS_USB_PHY_CFG_PLLCFG1 (0xc) > +#define EXYNOS_PHY_CFG_PLL_FB_DIV_11_8_MASK GENMASK(11, 8) > +#define EXYNOS_DIV_11_8_19_2_MHZ_VAL (0x0) > +#define EXYNOS_DIV_11_8_20_MHZ_VAL (0x0) > +#define EXYNOS_DIV_11_8_24_MHZ_VAL (0x0) > +#define EXYNOS_DIV_11_8_26_MHZ_VAL (0x0) > +#define EXYNOS_DIV_11_8_48_MHZ_VAL (0x1) > + > +#define EXYNOS_PHY_CFG_TX (0x14) > +#define EXYNOS_PHY_CFG_TX_FSLS_VREF_TUNE_MASK GENMASK(2, 1) > + > +#define EXYNOS_USB_PHY_UTMI_TESTSE (0x20) > +#define TEST_IDDQ BIT(6) > + > #define QCOM_USB_PHY_UTMI_CTRL0 (0x3c) > #define SLEEPM BIT(0) > #define OPMODE_MASK GENMASK(4, 3) > @@ -196,6 +229,93 @@ static void qcom_eusb2_default_parameters(struct snps_eusb2_hsphy *phy) > FIELD_PREP(PHY_CFG_TX_HS_XV_TUNE_MASK, 0x0)); > } > > +static int exynos_eusb2_ref_clk_init(struct snps_eusb2_hsphy *phy) > +{ > + unsigned long ref_clk_freq = clk_get_rate(phy->ref_clk); > + > + switch (ref_clk_freq) { > + case 19200000: > + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_HS_PHY_CTRL_COMMON, > + FSEL_MASK, > + FIELD_PREP(FSEL_MASK, FSEL_19_2_MHZ_VAL)); > + Could you please unify the switchcase? assign the values to temp variables, then program them from a single code stream. Or maybe even replace switch-case with a table-based lookup. (we probably should implement the similar change for qcom part. Maybe you can refactor it too?) Other than that LGTM. > + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_CFG_PLLCFG0, > + PHY_CFG_PLL_FB_DIV_19_8_MASK, > + FIELD_PREP(PHY_CFG_PLL_FB_DIV_19_8_MASK, > + DIV_19_8_19_2_MHZ_VAL)); > + > + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_CFG_PLLCFG1, > + EXYNOS_PHY_CFG_PLL_FB_DIV_11_8_MASK, > + EXYNOS_DIV_11_8_19_2_MHZ_VAL); > + break; > + > + case 20000000: > + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_HS_PHY_CTRL_COMMON, > + FSEL_MASK, > + FIELD_PREP(FSEL_MASK, FSEL_20_MHZ_VAL)); > + > + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_CFG_PLLCFG0, > + PHY_CFG_PLL_FB_DIV_19_8_MASK, > + FIELD_PREP(PHY_CFG_PLL_FB_DIV_19_8_MASK, > + DIV_19_8_20_MHZ_VAL)); > + > + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_CFG_PLLCFG1, > + EXYNOS_PHY_CFG_PLL_FB_DIV_11_8_MASK, > + EXYNOS_DIV_11_8_20_MHZ_VAL); > + break; > +
On 2/24/25 01:51, Dmitry Baryshkov wrote: > On Sun, Feb 23, 2025 at 02:22:26PM +0200, Ivaylo Ivanov wrote: >> The Exynos2200 SoC reuses the Synopsis eUSB2 PHY IP, alongside an >> external repeater, for USB 2.0. Add support for it to the existing >> driver. >> >> Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> >> --- >> drivers/phy/Kconfig | 2 +- >> drivers/phy/phy-snps-eusb2.c | 172 +++++++++++++++++++++++++++++++++++ >> 2 files changed, 173 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig >> index 11c166204..58c911e1b 100644 >> --- a/drivers/phy/Kconfig >> +++ b/drivers/phy/Kconfig >> @@ -45,7 +45,7 @@ config PHY_PISTACHIO_USB >> >> config PHY_SNPS_EUSB2 >> tristate "SNPS eUSB2 PHY Driver" >> - depends on OF && (ARCH_QCOM || COMPILE_TEST) >> + depends on OF && (ARCH_EXYNOS || ARCH_QCOM || COMPILE_TEST) >> select GENERIC_PHY >> help >> Enable support for the USB high-speed SNPS eUSB2 phy on select >> diff --git a/drivers/phy/phy-snps-eusb2.c b/drivers/phy/phy-snps-eusb2.c >> index 7a242fe32..67a19d671 100644 >> --- a/drivers/phy/phy-snps-eusb2.c >> +++ b/drivers/phy/phy-snps-eusb2.c >> @@ -13,6 +13,39 @@ >> #include <linux/regulator/consumer.h> >> #include <linux/reset.h> >> >> +#define EXYNOS_USB_PHY_HS_PHY_CTRL_RST (0x0) >> +#define USB_PHY_RST_MASK GENMASK(1, 0) >> +#define UTMI_PORT_RST_MASK GENMASK(5, 4) >> + >> +#define EXYNOS_USB_PHY_HS_PHY_CTRL_COMMON (0x4) >> +#define RPTR_MODE BIT(10) >> +#define FSEL_20_MHZ_VAL (0x1) >> +#define FSEL_24_MHZ_VAL (0x2) >> +#define FSEL_26_MHZ_VAL (0x3) >> +#define FSEL_48_MHZ_VAL (0x2) >> + >> +#define EXYNOS_USB_PHY_CFG_PLLCFG0 (0x8) >> +#define PHY_CFG_PLL_FB_DIV_19_8_MASK GENMASK(19, 8) >> +#define DIV_19_8_19_2_MHZ_VAL (0x170) >> +#define DIV_19_8_20_MHZ_VAL (0x160) >> +#define DIV_19_8_24_MHZ_VAL (0x120) >> +#define DIV_19_8_26_MHZ_VAL (0x107) >> +#define DIV_19_8_48_MHZ_VAL (0x120) >> + >> +#define EXYNOS_USB_PHY_CFG_PLLCFG1 (0xc) >> +#define EXYNOS_PHY_CFG_PLL_FB_DIV_11_8_MASK GENMASK(11, 8) >> +#define EXYNOS_DIV_11_8_19_2_MHZ_VAL (0x0) >> +#define EXYNOS_DIV_11_8_20_MHZ_VAL (0x0) >> +#define EXYNOS_DIV_11_8_24_MHZ_VAL (0x0) >> +#define EXYNOS_DIV_11_8_26_MHZ_VAL (0x0) >> +#define EXYNOS_DIV_11_8_48_MHZ_VAL (0x1) >> + >> +#define EXYNOS_PHY_CFG_TX (0x14) >> +#define EXYNOS_PHY_CFG_TX_FSLS_VREF_TUNE_MASK GENMASK(2, 1) >> + >> +#define EXYNOS_USB_PHY_UTMI_TESTSE (0x20) >> +#define TEST_IDDQ BIT(6) >> + >> #define QCOM_USB_PHY_UTMI_CTRL0 (0x3c) >> #define SLEEPM BIT(0) >> #define OPMODE_MASK GENMASK(4, 3) >> @@ -196,6 +229,93 @@ static void qcom_eusb2_default_parameters(struct snps_eusb2_hsphy *phy) >> FIELD_PREP(PHY_CFG_TX_HS_XV_TUNE_MASK, 0x0)); >> } >> >> +static int exynos_eusb2_ref_clk_init(struct snps_eusb2_hsphy *phy) >> +{ >> + unsigned long ref_clk_freq = clk_get_rate(phy->ref_clk); >> + >> + switch (ref_clk_freq) { >> + case 19200000: >> + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_HS_PHY_CTRL_COMMON, >> + FSEL_MASK, >> + FIELD_PREP(FSEL_MASK, FSEL_19_2_MHZ_VAL)); >> + > Could you please unify the switchcase? assign the values to temp > variables, then program them from a single code stream. Or maybe even > replace switch-case with a table-based lookup. > > (we probably should implement the similar change for qcom part. Maybe > you can refactor it too?) Alright. I'll do it for the Qualcomm part too in a separate commit. Thanks for the feedback! Best regards, Ivaylo > Other than that LGTM. > >> + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_CFG_PLLCFG0, >> + PHY_CFG_PLL_FB_DIV_19_8_MASK, >> + FIELD_PREP(PHY_CFG_PLL_FB_DIV_19_8_MASK, >> + DIV_19_8_19_2_MHZ_VAL)); >> + >> + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_CFG_PLLCFG1, >> + EXYNOS_PHY_CFG_PLL_FB_DIV_11_8_MASK, >> + EXYNOS_DIV_11_8_19_2_MHZ_VAL); >> + break; >> + >> + case 20000000: >> + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_HS_PHY_CTRL_COMMON, >> + FSEL_MASK, >> + FIELD_PREP(FSEL_MASK, FSEL_20_MHZ_VAL)); >> + >> + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_CFG_PLLCFG0, >> + PHY_CFG_PLL_FB_DIV_19_8_MASK, >> + FIELD_PREP(PHY_CFG_PLL_FB_DIV_19_8_MASK, >> + DIV_19_8_20_MHZ_VAL)); >> + >> + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_CFG_PLLCFG1, >> + EXYNOS_PHY_CFG_PLL_FB_DIV_11_8_MASK, >> + EXYNOS_DIV_11_8_20_MHZ_VAL); >> + break; >> +
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 11c166204..58c911e1b 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -45,7 +45,7 @@ config PHY_PISTACHIO_USB config PHY_SNPS_EUSB2 tristate "SNPS eUSB2 PHY Driver" - depends on OF && (ARCH_QCOM || COMPILE_TEST) + depends on OF && (ARCH_EXYNOS || ARCH_QCOM || COMPILE_TEST) select GENERIC_PHY help Enable support for the USB high-speed SNPS eUSB2 phy on select diff --git a/drivers/phy/phy-snps-eusb2.c b/drivers/phy/phy-snps-eusb2.c index 7a242fe32..67a19d671 100644 --- a/drivers/phy/phy-snps-eusb2.c +++ b/drivers/phy/phy-snps-eusb2.c @@ -13,6 +13,39 @@ #include <linux/regulator/consumer.h> #include <linux/reset.h> +#define EXYNOS_USB_PHY_HS_PHY_CTRL_RST (0x0) +#define USB_PHY_RST_MASK GENMASK(1, 0) +#define UTMI_PORT_RST_MASK GENMASK(5, 4) + +#define EXYNOS_USB_PHY_HS_PHY_CTRL_COMMON (0x4) +#define RPTR_MODE BIT(10) +#define FSEL_20_MHZ_VAL (0x1) +#define FSEL_24_MHZ_VAL (0x2) +#define FSEL_26_MHZ_VAL (0x3) +#define FSEL_48_MHZ_VAL (0x2) + +#define EXYNOS_USB_PHY_CFG_PLLCFG0 (0x8) +#define PHY_CFG_PLL_FB_DIV_19_8_MASK GENMASK(19, 8) +#define DIV_19_8_19_2_MHZ_VAL (0x170) +#define DIV_19_8_20_MHZ_VAL (0x160) +#define DIV_19_8_24_MHZ_VAL (0x120) +#define DIV_19_8_26_MHZ_VAL (0x107) +#define DIV_19_8_48_MHZ_VAL (0x120) + +#define EXYNOS_USB_PHY_CFG_PLLCFG1 (0xc) +#define EXYNOS_PHY_CFG_PLL_FB_DIV_11_8_MASK GENMASK(11, 8) +#define EXYNOS_DIV_11_8_19_2_MHZ_VAL (0x0) +#define EXYNOS_DIV_11_8_20_MHZ_VAL (0x0) +#define EXYNOS_DIV_11_8_24_MHZ_VAL (0x0) +#define EXYNOS_DIV_11_8_26_MHZ_VAL (0x0) +#define EXYNOS_DIV_11_8_48_MHZ_VAL (0x1) + +#define EXYNOS_PHY_CFG_TX (0x14) +#define EXYNOS_PHY_CFG_TX_FSLS_VREF_TUNE_MASK GENMASK(2, 1) + +#define EXYNOS_USB_PHY_UTMI_TESTSE (0x20) +#define TEST_IDDQ BIT(6) + #define QCOM_USB_PHY_UTMI_CTRL0 (0x3c) #define SLEEPM BIT(0) #define OPMODE_MASK GENMASK(4, 3) @@ -196,6 +229,93 @@ static void qcom_eusb2_default_parameters(struct snps_eusb2_hsphy *phy) FIELD_PREP(PHY_CFG_TX_HS_XV_TUNE_MASK, 0x0)); } +static int exynos_eusb2_ref_clk_init(struct snps_eusb2_hsphy *phy) +{ + unsigned long ref_clk_freq = clk_get_rate(phy->ref_clk); + + switch (ref_clk_freq) { + case 19200000: + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_HS_PHY_CTRL_COMMON, + FSEL_MASK, + FIELD_PREP(FSEL_MASK, FSEL_19_2_MHZ_VAL)); + + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_CFG_PLLCFG0, + PHY_CFG_PLL_FB_DIV_19_8_MASK, + FIELD_PREP(PHY_CFG_PLL_FB_DIV_19_8_MASK, + DIV_19_8_19_2_MHZ_VAL)); + + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_CFG_PLLCFG1, + EXYNOS_PHY_CFG_PLL_FB_DIV_11_8_MASK, + EXYNOS_DIV_11_8_19_2_MHZ_VAL); + break; + + case 20000000: + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_HS_PHY_CTRL_COMMON, + FSEL_MASK, + FIELD_PREP(FSEL_MASK, FSEL_20_MHZ_VAL)); + + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_CFG_PLLCFG0, + PHY_CFG_PLL_FB_DIV_19_8_MASK, + FIELD_PREP(PHY_CFG_PLL_FB_DIV_19_8_MASK, + DIV_19_8_20_MHZ_VAL)); + + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_CFG_PLLCFG1, + EXYNOS_PHY_CFG_PLL_FB_DIV_11_8_MASK, + EXYNOS_DIV_11_8_20_MHZ_VAL); + break; + + case 24000000: + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_HS_PHY_CTRL_COMMON, + FSEL_MASK, + FIELD_PREP(FSEL_MASK, FSEL_24_MHZ_VAL)); + + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_CFG_PLLCFG0, + PHY_CFG_PLL_FB_DIV_19_8_MASK, + FIELD_PREP(PHY_CFG_PLL_FB_DIV_19_8_MASK, + DIV_19_8_24_MHZ_VAL)); + + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_CFG_PLLCFG1, + EXYNOS_PHY_CFG_PLL_FB_DIV_11_8_MASK, + EXYNOS_DIV_11_8_24_MHZ_VAL); + break; + + case 26000000: + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_HS_PHY_CTRL_COMMON, + FSEL_MASK, + FIELD_PREP(FSEL_MASK, FSEL_26_MHZ_VAL)); + + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_CFG_PLLCFG0, + PHY_CFG_PLL_FB_DIV_19_8_MASK, + FIELD_PREP(PHY_CFG_PLL_FB_DIV_19_8_MASK, + DIV_19_8_26_MHZ_VAL)); + + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_CFG_PLLCFG1, + EXYNOS_PHY_CFG_PLL_FB_DIV_11_8_MASK, + EXYNOS_DIV_11_8_26_MHZ_VAL); + break; + + case 48000000: + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_HS_PHY_CTRL_COMMON, + FSEL_MASK, + FIELD_PREP(FSEL_MASK, FSEL_48_MHZ_VAL)); + + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_CFG_PLLCFG0, + PHY_CFG_PLL_FB_DIV_19_8_MASK, + FIELD_PREP(PHY_CFG_PLL_FB_DIV_19_8_MASK, + DIV_19_8_48_MHZ_VAL)); + + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_CFG_PLLCFG1, + EXYNOS_PHY_CFG_PLL_FB_DIV_11_8_MASK, + EXYNOS_DIV_11_8_48_MHZ_VAL); + break; + default: + dev_err(&phy->phy->dev, "unsupported ref_clk_freq:%lu\n", ref_clk_freq); + return -EINVAL; + } + + return 0; +} + static int qcom_eusb2_ref_clk_init(struct snps_eusb2_hsphy *phy) { unsigned long ref_clk_freq = clk_get_rate(phy->ref_clk); @@ -240,6 +360,55 @@ static int qcom_eusb2_ref_clk_init(struct snps_eusb2_hsphy *phy) return 0; } +static int exynos_snps_eusb2_hsphy_init(struct phy *p) +{ + struct snps_eusb2_hsphy *phy = phy_get_drvdata(p); + int ret; + + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_HS_PHY_CTRL_RST, + USB_PHY_RST_MASK | UTMI_PORT_RST_MASK, + USB_PHY_RST_MASK | UTMI_PORT_RST_MASK); + fsleep(50); /* required after holding phy in reset */ + + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_HS_PHY_CTRL_COMMON, + RPTR_MODE, RPTR_MODE); + + /* update ref_clk related registers */ + ret = exynos_eusb2_ref_clk_init(phy); + if (ret) + return ret; + + /* default parameter: tx fsls-vref */ + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_PHY_CFG_TX, + EXYNOS_PHY_CFG_TX_FSLS_VREF_TUNE_MASK, + FIELD_PREP(EXYNOS_PHY_CFG_TX_FSLS_VREF_TUNE_MASK, 0x0)); + + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_UTMI_TESTSE, + TEST_IDDQ, 0); + fsleep(10); /* required after releasing test_iddq */ + + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_HS_PHY_CTRL_RST, + USB_PHY_RST_MASK, 0); + + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_HS_PHY_CTRL_COMMON, + PHY_ENABLE, PHY_ENABLE); + + snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_HS_PHY_CTRL_RST, + UTMI_PORT_RST_MASK, 0); + + return 0; +} + +static const char * const exynos_eusb2_hsphy_clock_names[] = { + "ref", "bus", "ctrl", +}; + +static const struct snps_eusb2_phy_drvdata exynos2200_snps_eusb2_phy = { + .phy_init = exynos_snps_eusb2_hsphy_init, + .clk_names = exynos_eusb2_hsphy_clock_names, + .num_clks = ARRAY_SIZE(exynos_eusb2_hsphy_clock_names), +}; + static int qcom_snps_eusb2_hsphy_init(struct phy *p) { struct snps_eusb2_hsphy *phy = phy_get_drvdata(p); @@ -488,6 +657,9 @@ static const struct of_device_id snps_eusb2_hsphy_of_match_table[] = { { .compatible = "qcom,sm8550-snps-eusb2-phy", .data = &sm8550_snps_eusb2_phy, + }, { + .compatible = "samsung,exynos2200-snps-eusb2-phy", + .data = &exynos2200_snps_eusb2_phy, }, { }, }; MODULE_DEVICE_TABLE(of, snps_eusb2_hsphy_of_match_table);
The Exynos2200 SoC reuses the Synopsis eUSB2 PHY IP, alongside an external repeater, for USB 2.0. Add support for it to the existing driver. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> --- drivers/phy/Kconfig | 2 +- drivers/phy/phy-snps-eusb2.c | 172 +++++++++++++++++++++++++++++++++++ 2 files changed, 173 insertions(+), 1 deletion(-)