| Message ID | 20250224074143.767442-3-thippeswamy.havalige@amd.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add support for Versal Net CPM5N Root Port controller | expand |
On Mon, Feb 24, 2025 at 01:11:43PM +0530, Thippeswamy Havalige wrote: > The Versal Net ACAP (Adaptive Compute Acceleration Platform) devices > incorporate the Coherency and PCIe Gen5 Module, specifically the > Next-Generation Compact Module (CPM5NC). > > The integrated CPM5NC block, along with the built-in bridge, can function > as a PCIe Root Port & supports the PCIe Gen5 protocol with data transfer > rates of up to 32 GT/s, capable of supporting up to a x16 lane-width > configuration. > > Bridge errors are managed using a specific interrupt line designed for > CPM5N. INTx interrupt support is not available. > > Currently in this commit platform specific Bridge errors support is not > added. > > Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> One comment below which is not related to *this* patch, but should be fixed separately (ideally before this patch). > --- > Changes in v2: > - Update commit message. > Changes in v3: > - Address review comments. > --- > drivers/pci/controller/pcie-xilinx-cpm.c | 40 +++++++++++++++++------- > 1 file changed, 29 insertions(+), 11 deletions(-) > > diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c b/drivers/pci/controller/pcie-xilinx-cpm.c > index 81e8bfae53d0..a0815c5010d9 100644 > --- a/drivers/pci/controller/pcie-xilinx-cpm.c > +++ b/drivers/pci/controller/pcie-xilinx-cpm.c > @@ -84,6 +84,7 @@ enum xilinx_cpm_version { > CPM, > CPM5, > CPM5_HOST1, > + CPM5NC_HOST, > }; > > /** > @@ -478,6 +479,9 @@ static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port) > { > const struct xilinx_cpm_variant *variant = port->variant; > > + if (variant->version != CPM5NC_HOST) > + return; > + > if (cpm_pcie_link_up(port)) > dev_info(port->dev, "PCIe Link is UP\n"); > else > @@ -578,16 +582,18 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev) > > port->dev = dev; > > - err = xilinx_cpm_pcie_init_irq_domain(port); > - if (err) > - return err; > + port->variant = of_device_get_match_data(dev); > + > + if (port->variant->version != CPM5NC_HOST) { > + err = xilinx_cpm_pcie_init_irq_domain(port); > + if (err) > + return err; > + } > > bus = resource_list_first_type(&bridge->windows, IORESOURCE_BUS); > if (!bus) > return -ENODEV; Here, xilinx_cpm_free_irq_domains() should be called in the error path. - Mani
Hi Mani, Thanks for reviewing & I ll update below comment in next patch. Regards, Thippeswamy H -----Original Message----- From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Sent: Monday, February 24, 2025 1:37 PM To: Havalige, Thippeswamy <thippeswamy.havalige@amd.com> Cc: bhelgaas@google.com; lpieralisi@kernel.org; kw@linux.com; robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org; linux-pci@vger.kernel.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; Simek, Michal <michal.simek@amd.com>; Gogada, Bharat Kumar <bharat.kumar.gogada@amd.com> Subject: Re: [PATCH v4 2/2] PCI: xilinx-cpm: Add support for Versal Net CPM5NC Root Port controller On Mon, Feb 24, 2025 at 01:11:43PM +0530, Thippeswamy Havalige wrote: > The Versal Net ACAP (Adaptive Compute Acceleration Platform) devices > incorporate the Coherency and PCIe Gen5 Module, specifically the > Next-Generation Compact Module (CPM5NC). > > The integrated CPM5NC block, along with the built-in bridge, can function > as a PCIe Root Port & supports the PCIe Gen5 protocol with data transfer > rates of up to 32 GT/s, capable of supporting up to a x16 lane-width > configuration. > > Bridge errors are managed using a specific interrupt line designed for > CPM5N. INTx interrupt support is not available. > > Currently in this commit platform specific Bridge errors support is not > added. > > Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> One comment below which is not related to *this* patch, but should be fixed separately (ideally before this patch). > --- > Changes in v2: > - Update commit message. > Changes in v3: > - Address review comments. > --- > drivers/pci/controller/pcie-xilinx-cpm.c | 40 +++++++++++++++++------- > 1 file changed, 29 insertions(+), 11 deletions(-) > > diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c b/drivers/pci/controller/pcie-xilinx-cpm.c > index 81e8bfae53d0..a0815c5010d9 100644 > --- a/drivers/pci/controller/pcie-xilinx-cpm.c > +++ b/drivers/pci/controller/pcie-xilinx-cpm.c > @@ -84,6 +84,7 @@ enum xilinx_cpm_version { > CPM, > CPM5, > CPM5_HOST1, > + CPM5NC_HOST, > }; > > /** > @@ -478,6 +479,9 @@ static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port) > { > const struct xilinx_cpm_variant *variant = port->variant; > > + if (variant->version != CPM5NC_HOST) > + return; > + > if (cpm_pcie_link_up(port)) > dev_info(port->dev, "PCIe Link is UP\n"); > else > @@ -578,16 +582,18 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev) > > port->dev = dev; > > - err = xilinx_cpm_pcie_init_irq_domain(port); > - if (err) > - return err; > + port->variant = of_device_get_match_data(dev); > + > + if (port->variant->version != CPM5NC_HOST) { > + err = xilinx_cpm_pcie_init_irq_domain(port); > + if (err) > + return err; > + } > > bus = resource_list_first_type(&bridge->windows, IORESOURCE_BUS); > if (!bus) > return -ENODEV; Here, xilinx_cpm_free_irq_domains() should be called in the error path. - Mani
diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c b/drivers/pci/controller/pcie-xilinx-cpm.c index 81e8bfae53d0..a0815c5010d9 100644 --- a/drivers/pci/controller/pcie-xilinx-cpm.c +++ b/drivers/pci/controller/pcie-xilinx-cpm.c @@ -84,6 +84,7 @@ enum xilinx_cpm_version { CPM, CPM5, CPM5_HOST1, + CPM5NC_HOST, }; /** @@ -478,6 +479,9 @@ static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port) { const struct xilinx_cpm_variant *variant = port->variant; + if (variant->version != CPM5NC_HOST) + return; + if (cpm_pcie_link_up(port)) dev_info(port->dev, "PCIe Link is UP\n"); else @@ -578,16 +582,18 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev) port->dev = dev; - err = xilinx_cpm_pcie_init_irq_domain(port); - if (err) - return err; + port->variant = of_device_get_match_data(dev); + + if (port->variant->version != CPM5NC_HOST) { + err = xilinx_cpm_pcie_init_irq_domain(port); + if (err) + return err; + } bus = resource_list_first_type(&bridge->windows, IORESOURCE_BUS); if (!bus) return -ENODEV; - port->variant = of_device_get_match_data(dev); - err = xilinx_cpm_pcie_parse_dt(port, bus->res); if (err) { dev_err(dev, "Parsing DT failed\n"); @@ -596,10 +602,12 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev) xilinx_cpm_pcie_init_port(port); - err = xilinx_cpm_setup_irq(port); - if (err) { - dev_err(dev, "Failed to set up interrupts\n"); - goto err_setup_irq; + if (port->variant->version != CPM5NC_HOST) { + err = xilinx_cpm_setup_irq(port); + if (err) { + dev_err(dev, "Failed to set up interrupts\n"); + goto err_setup_irq; + } } bridge->sysdata = port->cfg; @@ -612,11 +620,13 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev) return 0; err_host_bridge: - xilinx_cpm_free_interrupts(port); + if (port->variant->version != CPM5NC_HOST) + xilinx_cpm_free_interrupts(port); err_setup_irq: pci_ecam_free(port->cfg); err_parse_dt: - xilinx_cpm_free_irq_domains(port); + if (port->variant->version != CPM5NC_HOST) + xilinx_cpm_free_irq_domains(port); return err; } @@ -639,6 +649,10 @@ static const struct xilinx_cpm_variant cpm5_host1 = { .ir_enable = XILINX_CPM_PCIE1_IR_ENABLE, }; +static const struct xilinx_cpm_variant cpm5n_host = { + .version = CPM5NC_HOST, +}; + static const struct of_device_id xilinx_cpm_pcie_of_match[] = { { .compatible = "xlnx,versal-cpm-host-1.00", @@ -652,6 +666,10 @@ static const struct of_device_id xilinx_cpm_pcie_of_match[] = { .compatible = "xlnx,versal-cpm5-host1", .data = &cpm5_host1, }, + { + .compatible = "xlnx,versal-cpm5nc-host", + .data = &cpm5n_host, + }, {} };
The Versal Net ACAP (Adaptive Compute Acceleration Platform) devices incorporate the Coherency and PCIe Gen5 Module, specifically the Next-Generation Compact Module (CPM5NC). The integrated CPM5NC block, along with the built-in bridge, can function as a PCIe Root Port & supports the PCIe Gen5 protocol with data transfer rates of up to 32 GT/s, capable of supporting up to a x16 lane-width configuration. Bridge errors are managed using a specific interrupt line designed for CPM5N. INTx interrupt support is not available. Currently in this commit platform specific Bridge errors support is not added. Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com> --- Changes in v2: - Update commit message. Changes in v3: - Address review comments. --- drivers/pci/controller/pcie-xilinx-cpm.c | 40 +++++++++++++++++------- 1 file changed, 29 insertions(+), 11 deletions(-)