| Message ID | 20250227110652.2342729-3-kever.yang@rock-chips.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [v2,1/3] dt-bindings: nvmem: rockchip,otp: Add support for rk3562 and rk3568 | expand |
On Thu, Feb 27, 2025 at 07:06:52PM +0800, Kever Yang wrote: > From: David Wu <david.wu@rock-chips.com> > > Use the phy_clk to prepare_enable and unprepare_disable related phy clock. > > Signed-off-by: David Wu <david.wu@rock-chips.com> > Signed-off-by: Kever Yang <kever.yang@rock-chips.com> > --- > > Changes in v2: None > > drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c > index ccf4ecdffad3..cc90c74ec70c 100644 > --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c > @@ -1867,12 +1867,14 @@ static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat) > clk_set_rate(bsp_priv->clk_mac, 50000000); > } > > - if (plat->phy_node && bsp_priv->integrated_phy) { > + if (plat->phy_node) { > bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0); > ret = PTR_ERR_OR_ZERO(bsp_priv->clk_phy); > if (ret) > return dev_err_probe(dev, ret, "Cannot get PHY clock\n"); > - clk_set_rate(bsp_priv->clk_phy, 50000000); > + /* If it is not integrated_phy, clk_phy is optional */ > + if (bsp_priv->integrated_phy) > + clk_set_rate(bsp_priv->clk_phy, 50000000); That does not look backwards compatible. Older DT blobs which don't have an integrated PHY won't have a clock in the node, so of_clk_get() will return an error, and this function then exits with an error code. Andrew --- pw-bot: cr
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c index ccf4ecdffad3..cc90c74ec70c 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c @@ -1867,12 +1867,14 @@ static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat) clk_set_rate(bsp_priv->clk_mac, 50000000); } - if (plat->phy_node && bsp_priv->integrated_phy) { + if (plat->phy_node) { bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0); ret = PTR_ERR_OR_ZERO(bsp_priv->clk_phy); if (ret) return dev_err_probe(dev, ret, "Cannot get PHY clock\n"); - clk_set_rate(bsp_priv->clk_phy, 50000000); + /* If it is not integrated_phy, clk_phy is optional */ + if (bsp_priv->integrated_phy) + clk_set_rate(bsp_priv->clk_phy, 50000000); } return 0;