| Message ID | E1tna0F-0052sS-Lr@rmk-PC.armlinux.org.uk (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | net: stmmac: cleanup transmit clock setting | expand |
On Thu, Feb 27, 2025 at 09:16:23AM +0000, Russell King (Oracle) wrote: > Several stmmac sub-drivers which support RGMII follow the same pattern. > They calculate the transmit clock rate, and then call clk_set_rate(). > > Analysis of several implementation documents suggests that the platform > is responsible for providing the transmit clock to the DWMAC core's > clk_tx_i. The expected rates are: > > 10Mbps 100Mbps 1Gbps > MII 2.5MHz 25MHz > RMII 2.5MHz 25MHz > GMII 125MHz > RGMI 2.5MHz 25MHz 125MHz > > It seems some platforms require this clock to be manually configured, > but there are outputs from the MAC core that indicate the speed, so a > platform may use these to automatically configure the clock. Thus, we > can't just provide one solution to configure this clock rate. > > Moreover, the clock may need to be derived from one of several sources > depending on the interface mode. > > Provide a platform hook that is passed the transmit clock, interface > mode and speed. > > Reviewed-by: Thierry Reding <treding@nvidia.com> > Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Andrew
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 424fa2fe31c6..e66cd6889728 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -928,6 +928,7 @@ static void stmmac_mac_link_up(struct phylink_config *config, struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); unsigned int flow_ctrl; u32 old_ctrl, ctrl; + int ret; if ((priv->plat->flags & STMMAC_FLAG_SERDES_UP_AFTER_PHY_LINKUP) && priv->plat->serdes_powerup) @@ -1020,6 +1021,16 @@ static void stmmac_mac_link_up(struct phylink_config *config, if (ctrl != old_ctrl) writel(ctrl, priv->ioaddr + MAC_CTRL_REG); + if (priv->plat->set_clk_tx_rate) { + ret = priv->plat->set_clk_tx_rate(priv->plat->bsp_priv, + priv->plat->clk_tx_i, + interface, speed); + if (ret < 0) + netdev_err(priv->dev, + "failed to configure transmit clock for %dMbps: %pe\n", + speed, ERR_PTR(ret)); + } + stmmac_mac_set(priv, priv->ioaddr, true); if (priv->dma_cap.eee) stmmac_set_eee_pls(priv, priv->hw, true); diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index 6d2aa77ea963..cd0d1383df87 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -78,6 +78,7 @@ | DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \ | DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256) +struct clk; struct stmmac_priv; /* Platfrom data for platform device structure's platform_data field */ @@ -231,6 +232,8 @@ struct plat_stmmacenet_data { u8 tx_sched_algorithm; struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES]; struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES]; + int (*set_clk_tx_rate)(void *priv, struct clk *clk_tx_i, + phy_interface_t interface, int speed); void (*fix_mac_speed)(void *priv, int speed, unsigned int mode); int (*fix_soc_reset)(void *priv, void __iomem *ioaddr); int (*serdes_powerup)(struct net_device *ndev, void *priv); @@ -252,6 +255,7 @@ struct plat_stmmacenet_data { struct clk *stmmac_clk; struct clk *pclk; struct clk *clk_ptp_ref; + struct clk *clk_tx_i; /* clk_tx_i to MAC core */ unsigned long clk_ptp_rate; unsigned long clk_ref_rate; struct clk_bulk_data *clks;