| Message ID | 20250227170012.124768-10-marex@denx.de (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: dts: imx95: Add support for Mali G310 GPU | expand |
On Thu, Feb 27, 2025 at 05:58:09PM +0100, Marek Vasut wrote: > The instance of the GPU populated in i.MX95 is the G310, > describe this GPU in the DT. Include description of the > GPUMIX block controller, which can be operated as a simple > reset. Include dummy GPU voltage regulator and OPP tables. > > Signed-off-by: Marek Vasut <marex@denx.de> > --- > Cc: Boris Brezillon <boris.brezillon@collabora.com> > Cc: Conor Dooley <conor+dt@kernel.org> > Cc: David Airlie <airlied@gmail.com> > Cc: Fabio Estevam <festevam@gmail.com> > Cc: Krzysztof Kozlowski <krzk+dt@kernel.org> > Cc: Liviu Dudau <liviu.dudau@arm.com> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> > Cc: Maxime Ripard <mripard@kernel.org> > Cc: Pengutronix Kernel Team <kernel@pengutronix.de> > Cc: Philipp Zabel <p.zabel@pengutronix.de> > Cc: Rob Herring <robh@kernel.org> > Cc: Sascha Hauer <s.hauer@pengutronix.de> > Cc: Sebastian Reichel <sre@kernel.org> > Cc: Shawn Guo <shawnguo@kernel.org> > Cc: Simona Vetter <simona@ffwll.ch> > Cc: Steven Price <steven.price@arm.com> > Cc: Thomas Zimmermann <tzimmermann@suse.de> > Cc: devicetree@vger.kernel.org > Cc: dri-devel@lists.freedesktop.org > Cc: imx@lists.linux.dev > Cc: linux-arm-kernel@lists.infradead.org > --- > arch/arm64/boot/dts/freescale/imx95.dtsi | 62 ++++++++++++++++++++++++ > 1 file changed, 62 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi > index 3af13173de4bd..36bad211e5558 100644 > --- a/arch/arm64/boot/dts/freescale/imx95.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi > @@ -249,6 +249,37 @@ dummy: clock-dummy { > clock-output-names = "dummy"; > }; > > + gpu_fixed_reg: fixed-gpu-reg { > + compatible = "regulator-fixed"; > + regulator-min-microvolt = <920000>; > + regulator-max-microvolt = <920000>; > + regulator-name = "vdd_gpu"; > + regulator-always-on; > + regulator-boot-on; Does really need regulator-boot-on and regulator-always-on ? > + }; > + > + gpu_opp_table: opp_table { > + compatible = "operating-points-v2"; > + > + opp-500000000 { > + opp-hz = /bits/ 64 <500000000>; > + opp-hz-real = /bits/ 64 <500000000>; > + opp-microvolt = <920000>; > + }; > + > + opp-800000000 { > + opp-hz = /bits/ 64 <800000000>; > + opp-hz-real = /bits/ 64 <800000000>; > + opp-microvolt = <920000>; > + }; > + > + opp-1000000000 { > + opp-hz = /bits/ 64 <1000000000>; > + opp-hz-real = /bits/ 64 <1000000000>; > + opp-microvolt = <920000>; > + }; > + }; > + > clk_ext1: clock-ext1 { > compatible = "fixed-clock"; > #clock-cells = <0>; > @@ -1846,6 +1877,37 @@ netc_emdio: mdio@0,0 { > }; > }; > > + gpu_blk_ctrl: reset-controller@4d810000 { > + compatible = "fsl,imx95-gpu-blk-ctrl"; > + reg = <0x0 0x4d810000 0x0 0xc>; > + #reset-cells = <1>; > + clocks = <&scmi_clk IMX95_CLK_GPUAPB>; > + assigned-clocks = <&scmi_clk IMX95_CLK_GPUAPB>; > + assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; > + assigned-clock-rates = <133333333>; > + power-domains = <&scmi_devpd IMX95_PD_GPU>; > + status = "disabled"; > + }; > + > + gpu: gpu@4d900000 { > + compatible = "fsl,imx95-mali", "arm,mali-valhall-csf"; > + reg = <0 0x4d900000 0 0x480000>; > + clocks = <&scmi_clk IMX95_CLK_GPU>; > + clock-names = "core"; > + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "gpu", "job", "mmu"; > + mali-supply = <&gpu_fixed_reg>; > + operating-points-v2 = <&gpu_opp_table>; > + power-domains = <&scmi_devpd IMX95_PD_GPU>, <&scmi_perf IMX95_PERF_GPU>; > + power-domain-names = "mix", "perf"; > + resets = <&gpu_blk_ctrl 0>; > + #cooling-cells = <2>; > + dynamic-power-coefficient = <1013>; > + status = "disabled"; GPU is internal module, which have not much dependence with other module such as pinmux. why not default status is "disabled". Supposed gpu driver will turn off clock and power if not used. Frank > + }; > + > ddr-pmu@4e090dc0 { > compatible = "fsl,imx95-ddr-pmu", "fsl,imx93-ddr-pmu"; > reg = <0x0 0x4e090dc0 0x0 0x200>; > -- > 2.47.2 >
On 2/27/25 6:43 PM, Frank Li wrote: [...] >> diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi >> index 3af13173de4bd..36bad211e5558 100644 >> --- a/arch/arm64/boot/dts/freescale/imx95.dtsi >> +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi >> @@ -249,6 +249,37 @@ dummy: clock-dummy { >> clock-output-names = "dummy"; >> }; >> >> + gpu_fixed_reg: fixed-gpu-reg { >> + compatible = "regulator-fixed"; >> + regulator-min-microvolt = <920000>; >> + regulator-max-microvolt = <920000>; >> + regulator-name = "vdd_gpu"; >> + regulator-always-on; >> + regulator-boot-on; > > Does really need regulator-boot-on and regulator-always-on ? I don't think so, this is a development remnant, fixed, thanks. [...] >> + gpu: gpu@4d900000 { >> + compatible = "fsl,imx95-mali", "arm,mali-valhall-csf"; >> + reg = <0 0x4d900000 0 0x480000>; >> + clocks = <&scmi_clk IMX95_CLK_GPU>; >> + clock-names = "core"; >> + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "gpu", "job", "mmu"; >> + mali-supply = <&gpu_fixed_reg>; >> + operating-points-v2 = <&gpu_opp_table>; >> + power-domains = <&scmi_devpd IMX95_PD_GPU>, <&scmi_perf IMX95_PERF_GPU>; >> + power-domain-names = "mix", "perf"; >> + resets = <&gpu_blk_ctrl 0>; >> + #cooling-cells = <2>; >> + dynamic-power-coefficient = <1013>; >> + status = "disabled"; > > GPU is internal module, which have not much dependence with other module > such as pinmux. why not default status is "disabled". Supposed gpu driver > will turn off clock and power if not used. My thinking was that there are MX95 SoC with GPU fused off, hence it is better to keep the GPU disabled in DT by default. But I can also keep it enabled and the few boards which do not have MX95 SoC with GPU can explicitly disable it in board DT. What do you think ?
On Thu, Feb 27, 2025 at 09:36:55PM +0100, Marek Vasut wrote: > On 2/27/25 6:43 PM, Frank Li wrote: > [...] > > > > diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi > > > index 3af13173de4bd..36bad211e5558 100644 > > > --- a/arch/arm64/boot/dts/freescale/imx95.dtsi > > > +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi > > > @@ -249,6 +249,37 @@ dummy: clock-dummy { > > > clock-output-names = "dummy"; > > > }; > > > > > > + gpu_fixed_reg: fixed-gpu-reg { > > > + compatible = "regulator-fixed"; > > > + regulator-min-microvolt = <920000>; > > > + regulator-max-microvolt = <920000>; > > > + regulator-name = "vdd_gpu"; > > > + regulator-always-on; > > > + regulator-boot-on; > > > > Does really need regulator-boot-on and regulator-always-on ? > > I don't think so, this is a development remnant, fixed, thanks. > > [...] > > > > + gpu: gpu@4d900000 { > > > + compatible = "fsl,imx95-mali", "arm,mali-valhall-csf"; > > > + reg = <0 0x4d900000 0 0x480000>; > > > + clocks = <&scmi_clk IMX95_CLK_GPU>; > > > + clock-names = "core"; > > > + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; > > > + interrupt-names = "gpu", "job", "mmu"; > > > + mali-supply = <&gpu_fixed_reg>; > > > + operating-points-v2 = <&gpu_opp_table>; > > > + power-domains = <&scmi_devpd IMX95_PD_GPU>, <&scmi_perf IMX95_PERF_GPU>; > > > + power-domain-names = "mix", "perf"; > > > + resets = <&gpu_blk_ctrl 0>; > > > + #cooling-cells = <2>; > > > + dynamic-power-coefficient = <1013>; > > > + status = "disabled"; > > > > GPU is internal module, which have not much dependence with other module > > such as pinmux. why not default status is "disabled". Supposed gpu driver > > will turn off clock and power if not used. > My thinking was that there are MX95 SoC with GPU fused off, hence it is > better to keep the GPU disabled in DT by default. But I can also keep it > enabled and the few boards which do not have MX95 SoC with GPU can > explicitly disable it in board DT. > > What do you think ? GPU Fuse off should use access-control, see thread https://lore.kernel.org/imx/20250207120213.GD14860@localhost.localdomain/ Frank
On 2/27/25 10:27 PM, Frank Li wrote: [...] >>>> + gpu: gpu@4d900000 { >>>> + compatible = "fsl,imx95-mali", "arm,mali-valhall-csf"; >>>> + reg = <0 0x4d900000 0 0x480000>; >>>> + clocks = <&scmi_clk IMX95_CLK_GPU>; >>>> + clock-names = "core"; >>>> + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; >>>> + interrupt-names = "gpu", "job", "mmu"; >>>> + mali-supply = <&gpu_fixed_reg>; >>>> + operating-points-v2 = <&gpu_opp_table>; >>>> + power-domains = <&scmi_devpd IMX95_PD_GPU>, <&scmi_perf IMX95_PERF_GPU>; >>>> + power-domain-names = "mix", "perf"; >>>> + resets = <&gpu_blk_ctrl 0>; >>>> + #cooling-cells = <2>; >>>> + dynamic-power-coefficient = <1013>; >>>> + status = "disabled"; >>> >>> GPU is internal module, which have not much dependence with other module >>> such as pinmux. why not default status is "disabled". Supposed gpu driver >>> will turn off clock and power if not used. >> My thinking was that there are MX95 SoC with GPU fused off, hence it is >> better to keep the GPU disabled in DT by default. But I can also keep it >> enabled and the few boards which do not have MX95 SoC with GPU can >> explicitly disable it in board DT. >> >> What do you think ? > > GPU Fuse off should use access-control, see thread > https://lore.kernel.org/imx/20250207120213.GD14860@localhost.localdomain/ Did that thread ever go anywhere ? It seems there is no real conclusion, is there ? +Cc Alex .
On Thu, Feb 27, 2025 at 10:34:20PM +0100, Marek Vasut wrote: > On 2/27/25 10:27 PM, Frank Li wrote: > > [...] > > > > > > + gpu: gpu@4d900000 { > > > > > + compatible = "fsl,imx95-mali", "arm,mali-valhall-csf"; > > > > > + reg = <0 0x4d900000 0 0x480000>; > > > > > + clocks = <&scmi_clk IMX95_CLK_GPU>; > > > > > + clock-names = "core"; > > > > > + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, > > > > > + <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, > > > > > + <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; > > > > > + interrupt-names = "gpu", "job", "mmu"; > > > > > + mali-supply = <&gpu_fixed_reg>; > > > > > + operating-points-v2 = <&gpu_opp_table>; > > > > > + power-domains = <&scmi_devpd IMX95_PD_GPU>, <&scmi_perf IMX95_PERF_GPU>; > > > > > + power-domain-names = "mix", "perf"; > > > > > + resets = <&gpu_blk_ctrl 0>; > > > > > + #cooling-cells = <2>; > > > > > + dynamic-power-coefficient = <1013>; > > > > > + status = "disabled"; > > > > > > > > GPU is internal module, which have not much dependence with other module > > > > such as pinmux. why not default status is "disabled". Supposed gpu driver > > > > will turn off clock and power if not used. > > > My thinking was that there are MX95 SoC with GPU fused off, hence it is > > > better to keep the GPU disabled in DT by default. But I can also keep it > > > enabled and the few boards which do not have MX95 SoC with GPU can > > > explicitly disable it in board DT. > > > > > > What do you think ? > > > > GPU Fuse off should use access-control, see thread > > https://lore.kernel.org/imx/20250207120213.GD14860@localhost.localdomain/ > Did that thread ever go anywhere ? It seems there is no real conclusion, is > there ? +Cc Alex . The direction is use access-control to indicate fuse disable. Only implement detail is under discussion. Frank
Hi Marek, Am Donnerstag, 27. Februar 2025, 17:58:09 CET schrieb Marek Vasut: > The instance of the GPU populated in i.MX95 is the G310, > describe this GPU in the DT. Include description of the > GPUMIX block controller, which can be operated as a simple > reset. Include dummy GPU voltage regulator and OPP tables. > > Signed-off-by: Marek Vasut <marex@denx.de> > --- > Cc: Boris Brezillon <boris.brezillon@collabora.com> > Cc: Conor Dooley <conor+dt@kernel.org> > Cc: David Airlie <airlied@gmail.com> > Cc: Fabio Estevam <festevam@gmail.com> > Cc: Krzysztof Kozlowski <krzk+dt@kernel.org> > Cc: Liviu Dudau <liviu.dudau@arm.com> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> > Cc: Maxime Ripard <mripard@kernel.org> > Cc: Pengutronix Kernel Team <kernel@pengutronix.de> > Cc: Philipp Zabel <p.zabel@pengutronix.de> > Cc: Rob Herring <robh@kernel.org> > Cc: Sascha Hauer <s.hauer@pengutronix.de> > Cc: Sebastian Reichel <sre@kernel.org> > Cc: Shawn Guo <shawnguo@kernel.org> > Cc: Simona Vetter <simona@ffwll.ch> > Cc: Steven Price <steven.price@arm.com> > Cc: Thomas Zimmermann <tzimmermann@suse.de> > Cc: devicetree@vger.kernel.org > Cc: dri-devel@lists.freedesktop.org > Cc: imx@lists.linux.dev > Cc: linux-arm-kernel@lists.infradead.org > --- > arch/arm64/boot/dts/freescale/imx95.dtsi | 62 ++++++++++++++++++++++++ > 1 file changed, 62 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi > index 3af13173de4bd..36bad211e5558 100644 > --- a/arch/arm64/boot/dts/freescale/imx95.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi > @@ -249,6 +249,37 @@ dummy: clock-dummy { > clock-output-names = "dummy"; > }; > > + gpu_fixed_reg: fixed-gpu-reg { > + compatible = "regulator-fixed"; > + regulator-min-microvolt = <920000>; > + regulator-max-microvolt = <920000>; > + regulator-name = "vdd_gpu"; > + regulator-always-on; > + regulator-boot-on; > + }; Is this an internal voltage? > + > + gpu_opp_table: opp_table { Node-Names use dash instead of underscore. > + compatible = "operating-points-v2"; > + > + opp-500000000 { > + opp-hz = /bits/ 64 <500000000>; > + opp-hz-real = /bits/ 64 <500000000>; > + opp-microvolt = <920000>; > + }; > + > + opp-800000000 { > + opp-hz = /bits/ 64 <800000000>; > + opp-hz-real = /bits/ 64 <800000000>; > + opp-microvolt = <920000>; > + }; > + > + opp-1000000000 { > + opp-hz = /bits/ 64 <1000000000>; > + opp-hz-real = /bits/ 64 <1000000000>; > + opp-microvolt = <920000>; > + }; > + }; > + > clk_ext1: clock-ext1 { > compatible = "fixed-clock"; > #clock-cells = <0>; > @@ -1846,6 +1877,37 @@ netc_emdio: mdio@0,0 { > }; > }; > > + gpu_blk_ctrl: reset-controller@4d810000 { > + compatible = "fsl,imx95-gpu-blk-ctrl"; > + reg = <0x0 0x4d810000 0x0 0xc>; Mh, GPU_BLK_CTRL is /just a bit) more than the GPU reset. Does it make sense to make this an gpu-reset-only node, located at 0x4d810008? > + #reset-cells = <1>; > + clocks = <&scmi_clk IMX95_CLK_GPUAPB>; > + assigned-clocks = <&scmi_clk IMX95_CLK_GPUAPB>; > + assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; > + assigned-clock-rates = <133333333>; > + power-domains = <&scmi_devpd IMX95_PD_GPU>; > + status = "disabled"; > + }; > + > + gpu: gpu@4d900000 { > + compatible = "fsl,imx95-mali", "arm,mali-valhall-csf"; > + reg = <0 0x4d900000 0 0x480000>; > + clocks = <&scmi_clk IMX95_CLK_GPU>; There is also IMX95_CLK_GPUAPB. Is this only required for the rese control above? > + clock-names = "core"; > + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "gpu", "job", "mmu"; DT bindings say this order: job, mmu, gpu Best regards Alexander > + mali-supply = <&gpu_fixed_reg>; > + operating-points-v2 = <&gpu_opp_table>; > + power-domains = <&scmi_devpd IMX95_PD_GPU>, <&scmi_perf IMX95_PERF_GPU>; > + power-domain-names = "mix", "perf"; > + resets = <&gpu_blk_ctrl 0>; > + #cooling-cells = <2>; > + dynamic-power-coefficient = <1013>; > + status = "disabled"; > + }; > + > ddr-pmu@4e090dc0 { > compatible = "fsl,imx95-ddr-pmu", "fsl,imx93-ddr-pmu"; > reg = <0x0 0x4e090dc0 0x0 0x200>; >
Am Donnerstag, 27. Februar 2025, 23:21:22 CET schrieb Frank Li: > On Thu, Feb 27, 2025 at 10:34:20PM +0100, Marek Vasut wrote: > > On 2/27/25 10:27 PM, Frank Li wrote: > > > > [...] > > > > > > > > + gpu: gpu@4d900000 { > > > > > > + compatible = "fsl,imx95-mali", "arm,mali-valhall-csf"; > > > > > > + reg = <0 0x4d900000 0 0x480000>; > > > > > > + clocks = <&scmi_clk IMX95_CLK_GPU>; > > > > > > + clock-names = "core"; > > > > > > + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, > > > > > > + <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, > > > > > > + <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; > > > > > > + interrupt-names = "gpu", "job", "mmu"; > > > > > > + mali-supply = <&gpu_fixed_reg>; > > > > > > + operating-points-v2 = <&gpu_opp_table>; > > > > > > + power-domains = <&scmi_devpd IMX95_PD_GPU>, <&scmi_perf IMX95_PERF_GPU>; > > > > > > + power-domain-names = "mix", "perf"; > > > > > > + resets = <&gpu_blk_ctrl 0>; > > > > > > + #cooling-cells = <2>; > > > > > > + dynamic-power-coefficient = <1013>; > > > > > > + status = "disabled"; > > > > > > > > > > GPU is internal module, which have not much dependence with other module > > > > > such as pinmux. why not default status is "disabled". Supposed gpu driver > > > > > will turn off clock and power if not used. > > > > My thinking was that there are MX95 SoC with GPU fused off, hence it is > > > > better to keep the GPU disabled in DT by default. But I can also keep it > > > > enabled and the few boards which do not have MX95 SoC with GPU can > > > > explicitly disable it in board DT. > > > > > > > > What do you think ? > > > > > > GPU Fuse off should use access-control, see thread > > > https://lore.kernel.org/imx/20250207120213.GD14860@localhost.localdomain/ > > Did that thread ever go anywhere ? It seems there is no real conclusion, is > > there ? +Cc Alex . > > The direction is use access-control to indicate fuse disable. Only > implement detail is under discussion. Well, the discussion ended up to be more complicated for i.MX8M. For i.MX95 things are a bit easier, as fuses and clocks are controlled by System Manager (SM), accessed using SCMI. [1] is more important for imx95. Best regards Alexander [1] https://lore.kernel.org/all/20250204-imx-ocotp-v8-0-01be4a4bb045@nxp.com/
diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index 3af13173de4bd..36bad211e5558 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -249,6 +249,37 @@ dummy: clock-dummy { clock-output-names = "dummy"; }; + gpu_fixed_reg: fixed-gpu-reg { + compatible = "regulator-fixed"; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <920000>; + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + }; + + gpu_opp_table: opp_table { + compatible = "operating-points-v2"; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-hz-real = /bits/ 64 <500000000>; + opp-microvolt = <920000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-hz-real = /bits/ 64 <800000000>; + opp-microvolt = <920000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-hz-real = /bits/ 64 <1000000000>; + opp-microvolt = <920000>; + }; + }; + clk_ext1: clock-ext1 { compatible = "fixed-clock"; #clock-cells = <0>; @@ -1846,6 +1877,37 @@ netc_emdio: mdio@0,0 { }; }; + gpu_blk_ctrl: reset-controller@4d810000 { + compatible = "fsl,imx95-gpu-blk-ctrl"; + reg = <0x0 0x4d810000 0x0 0xc>; + #reset-cells = <1>; + clocks = <&scmi_clk IMX95_CLK_GPUAPB>; + assigned-clocks = <&scmi_clk IMX95_CLK_GPUAPB>; + assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; + assigned-clock-rates = <133333333>; + power-domains = <&scmi_devpd IMX95_PD_GPU>; + status = "disabled"; + }; + + gpu: gpu@4d900000 { + compatible = "fsl,imx95-mali", "arm,mali-valhall-csf"; + reg = <0 0x4d900000 0 0x480000>; + clocks = <&scmi_clk IMX95_CLK_GPU>; + clock-names = "core"; + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gpu", "job", "mmu"; + mali-supply = <&gpu_fixed_reg>; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&scmi_devpd IMX95_PD_GPU>, <&scmi_perf IMX95_PERF_GPU>; + power-domain-names = "mix", "perf"; + resets = <&gpu_blk_ctrl 0>; + #cooling-cells = <2>; + dynamic-power-coefficient = <1013>; + status = "disabled"; + }; + ddr-pmu@4e090dc0 { compatible = "fsl,imx95-ddr-pmu", "fsl,imx93-ddr-pmu"; reg = <0x0 0x4e090dc0 0x0 0x200>;
The instance of the GPU populated in i.MX95 is the G310, describe this GPU in the DT. Include description of the GPUMIX block controller, which can be operated as a simple reset. Include dummy GPU voltage regulator and OPP tables. Signed-off-by: Marek Vasut <marex@denx.de> --- Cc: Boris Brezillon <boris.brezillon@collabora.com> Cc: Conor Dooley <conor+dt@kernel.org> Cc: David Airlie <airlied@gmail.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org> Cc: Liviu Dudau <liviu.dudau@arm.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Maxime Ripard <mripard@kernel.org> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: Rob Herring <robh@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Sebastian Reichel <sre@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Simona Vetter <simona@ffwll.ch> Cc: Steven Price <steven.price@arm.com> Cc: Thomas Zimmermann <tzimmermann@suse.de> Cc: devicetree@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: imx@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org --- arch/arm64/boot/dts/freescale/imx95.dtsi | 62 ++++++++++++++++++++++++ 1 file changed, 62 insertions(+)