| Message ID | 20250304064710.2128993-3-jamin_lin@aspeedtech.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Fix hw-strap for AST2700 | expand |
On 3/4/25 07:47, Jamin Lin wrote: > According to the design of the AST2600, it has a Silicon Revision ID Register, > specifically SCU004 and SCU014, to set the Revision ID for the AST2600. > For the AST2600 A3, SCU004 is set to 0x05030303 and SCU014 is set to 0x05030303. > In the "aspeed_ast2600_scu_reset" function, the hardcoded value > "AST2600_A3_SILICON_REV" is set in SCU004, and "s->silicon_rev" is set in > SCU014. The value of "s->silicon_rev" is set by the SOC layer via the > "silicon-rev" property. > > However, the design of the AST2700 is different. There are two SCU controllers: > SCU0 (CPU Die) and SCU1 (IO Die). In the AST2700, the firmware reads the SCU > Silicon Revision ID register (SCU0_000) and the SCUIO Silicon Revision ID > register (SCU1_000), combining them into a single 64-bit value. > > The upper 32 bits represent the SCUIO, while the lower 32 bits correspond to the > SCU. For example, the AST2700-A1 revision is represented as 0x0601010306010103. > SCUIO_000 occupies bits [63:32] with a value of 0x06010103 and SCU_000 occupies > bits [31:0] with a value of 0x06010103. > > Reference: > https://github.com/AspeedTech-BMC/u-boot/blob/aspeed-master-v2023.10/arch/arm/mach-aspeed/ast2700/cpu-info.c > > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Thanks, C. > --- > hw/misc/aspeed_scu.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c > index 50f74fbabd..545d004749 100644 > --- a/hw/misc/aspeed_scu.c > +++ b/hw/misc/aspeed_scu.c > @@ -910,7 +910,6 @@ static const MemoryRegionOps aspeed_ast2700_scu_ops = { > }; > > static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = { > - [AST2700_SILICON_REV] = AST2700_A0_SILICON_REV, > [AST2700_HW_STRAP1] = 0x00000800, > [AST2700_HW_STRAP1_CLR] = 0xFFF0FFF0, > [AST2700_HW_STRAP1_LOCK] = 0x00000FFF, > @@ -940,6 +939,7 @@ static void aspeed_ast2700_scu_reset(DeviceState *dev) > AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev); > > memcpy(s->regs, asc->resets, asc->nr_regs * 4); > + s->regs[AST2700_SILICON_REV] = s->silicon_rev; > } > > static void aspeed_2700_scu_class_init(ObjectClass *klass, void *data) > @@ -1032,7 +1032,6 @@ static const MemoryRegionOps aspeed_ast2700_scuio_ops = { > }; > > static const uint32_t ast2700_a0_resets_io[ASPEED_AST2700_SCU_NR_REGS] = { > - [AST2700_SILICON_REV] = 0x06000003, > [AST2700_HW_STRAP1] = 0x00000504, > [AST2700_HW_STRAP1_CLR] = 0xFFF0FFF0, > [AST2700_HW_STRAP1_LOCK] = 0x00000FFF,
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 50f74fbabd..545d004749 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -910,7 +910,6 @@ static const MemoryRegionOps aspeed_ast2700_scu_ops = { }; static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = { - [AST2700_SILICON_REV] = AST2700_A0_SILICON_REV, [AST2700_HW_STRAP1] = 0x00000800, [AST2700_HW_STRAP1_CLR] = 0xFFF0FFF0, [AST2700_HW_STRAP1_LOCK] = 0x00000FFF, @@ -940,6 +939,7 @@ static void aspeed_ast2700_scu_reset(DeviceState *dev) AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev); memcpy(s->regs, asc->resets, asc->nr_regs * 4); + s->regs[AST2700_SILICON_REV] = s->silicon_rev; } static void aspeed_2700_scu_class_init(ObjectClass *klass, void *data) @@ -1032,7 +1032,6 @@ static const MemoryRegionOps aspeed_ast2700_scuio_ops = { }; static const uint32_t ast2700_a0_resets_io[ASPEED_AST2700_SCU_NR_REGS] = { - [AST2700_SILICON_REV] = 0x06000003, [AST2700_HW_STRAP1] = 0x00000504, [AST2700_HW_STRAP1_CLR] = 0xFFF0FFF0, [AST2700_HW_STRAP1_LOCK] = 0x00000FFF,
According to the design of the AST2600, it has a Silicon Revision ID Register, specifically SCU004 and SCU014, to set the Revision ID for the AST2600. For the AST2600 A3, SCU004 is set to 0x05030303 and SCU014 is set to 0x05030303. In the "aspeed_ast2600_scu_reset" function, the hardcoded value "AST2600_A3_SILICON_REV" is set in SCU004, and "s->silicon_rev" is set in SCU014. The value of "s->silicon_rev" is set by the SOC layer via the "silicon-rev" property. However, the design of the AST2700 is different. There are two SCU controllers: SCU0 (CPU Die) and SCU1 (IO Die). In the AST2700, the firmware reads the SCU Silicon Revision ID register (SCU0_000) and the SCUIO Silicon Revision ID register (SCU1_000), combining them into a single 64-bit value. The upper 32 bits represent the SCUIO, while the lower 32 bits correspond to the SCU. For example, the AST2700-A1 revision is represented as 0x0601010306010103. SCUIO_000 occupies bits [63:32] with a value of 0x06010103 and SCU_000 occupies bits [31:0] with a value of 0x06010103. Reference: https://github.com/AspeedTech-BMC/u-boot/blob/aspeed-master-v2023.10/arch/arm/mach-aspeed/ast2700/cpu-info.c Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> --- hw/misc/aspeed_scu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)