| Message ID | 20250317-fix-nexus-4-v1-8-655c52e2ad97@oss.qualcomm.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | ARM: qcom: fix APQ8064 schema warnings | expand |
On 3/17/25 6:44 PM, Dmitry Baryshkov wrote: > Use new SoC-specific compatible to the SPS SIC in addition to the > "syscon" compatible and rename the node to follow the purpose of it. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> > --- > arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi > index 522387700fc8ce854c0995636998d2d4237e33df..a106f9f984fcb51dea1fff1515e6f290b36ccf99 100644 > --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi > +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi > @@ -402,8 +402,8 @@ saw3_vreg: regulator { > }; > }; > > - sps_sic_non_secure: sps-sic-non-secure@12100000 { > - compatible = "syscon"; > + sps_sic_non_secure: interrupt-controller@12100000 { The register that the consumer of this points to doesn't seem to exist.. Konrad
On Tue, Mar 18, 2025 at 01:13:23PM +0100, Konrad Dybcio wrote: > On 3/17/25 6:44 PM, Dmitry Baryshkov wrote: > > Use new SoC-specific compatible to the SPS SIC in addition to the > > "syscon" compatible and rename the node to follow the purpose of it. > > > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> > > --- > > arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi > > index 522387700fc8ce854c0995636998d2d4237e33df..a106f9f984fcb51dea1fff1515e6f290b36ccf99 100644 > > --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi > > +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi > > @@ -402,8 +402,8 @@ saw3_vreg: regulator { > > }; > > }; > > > > - sps_sic_non_secure: sps-sic-non-secure@12100000 { > > - compatible = "syscon"; > > + sps_sic_non_secure: interrupt-controller@12100000 { > > The register that the consumer of this points to doesn't seem to exist.. It does, although it is marked as reserved. And this matches msm-3.4: .smsm_int.out_bit_pos = 1, .smsm_int.out_base = (void __iomem *)MSM_SIC_NON_SECURE_BASE, .smsm_int.out_offset = 0x4094, #define MSM_SIC_NON_SECURE_BASE IOMEM(0xFA600000) #define MSM_SIC_NON_SECURE_PHYS 0x12100000 #define MSM_SIC_NON_SECURE_SIZE SZ_64K I don't think anybody tried bringing up dsps on APQ8064 though.
diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index 522387700fc8ce854c0995636998d2d4237e33df..a106f9f984fcb51dea1fff1515e6f290b36ccf99 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -402,8 +402,8 @@ saw3_vreg: regulator { }; }; - sps_sic_non_secure: sps-sic-non-secure@12100000 { - compatible = "syscon"; + sps_sic_non_secure: interrupt-controller@12100000 { + compatible = "qcom,apq8064-sps-sic", "syscon"; reg = <0x12100000 0x10000>; };
Use new SoC-specific compatible to the SPS SIC in addition to the "syscon" compatible and rename the node to follow the purpose of it. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)