| Message ID | 20250327014717.2988633-2-terry.bowman@amd.com |
|---|---|
| State | New |
| Headers | show |
| Series | Enable CXL PCIe port protocol error handling and logging | expand |
Terry Bowman wrote: > CXL and AER drivers need the ability to identify CXL devices. > > Add set_pcie_cxl() with logic checking for CXL Flexbus DVSEC presence. The > CXL Flexbus DVSEC presence is used because it is required for all the CXL > PCIe devices.[1] > > Add boolean 'struct pci_dev::is_cxl' with the purpose to cache the CXL > Flexbus presence. > > Add function pcie_is_cxl() to return 'struct pci_dev::is_cxl'. > > [1] CXL 3.1 Spec, 8.1.1 PCIe Designated Vendor-Specific Extended > Capability (DVSEC) ID Assignment, Table 8-2 > > Signed-off-by: Terry Bowman <terry.bowman@amd.com> > --- > drivers/pci/pci.c | 5 +++++ > drivers/pci/probe.c | 10 ++++++++++ > include/linux/pci.h | 3 +++ > include/uapi/linux/pci_regs.h | 8 +++++++- > 4 files changed, 25 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c > index 869d204a70a3..a1d75f40017e 100644 > --- a/drivers/pci/pci.c > +++ b/drivers/pci/pci.c > @@ -5032,6 +5032,11 @@ static u16 cxl_port_dvsec(struct pci_dev *dev) > PCI_DVSEC_CXL_PORT); > } > > +inline bool pcie_is_cxl(struct pci_dev *pci_dev) > +{ > + return pci_dev->is_cxl; > +} Shouldn't this just be a static inline in include/linux/pci.h? > + > static bool cxl_sbr_masked(struct pci_dev *dev) > { > u16 dvsec, reg; [snip] > @@ -741,6 +742,8 @@ static inline bool pci_is_vga(struct pci_dev *pdev) > return false; > } > > +bool pcie_is_cxl(struct pci_dev *pci_dev); > + > #define for_each_pci_bridge(dev, bus) \ > list_for_each_entry(dev, &bus->devices, bus_list) \ > if (!pci_is_bridge(dev)) {} else > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > index 3445c4970e4d..7ccb3b2fcc38 100644 > --- a/include/uapi/linux/pci_regs.h > +++ b/include/uapi/linux/pci_regs.h > @@ -1208,9 +1208,15 @@ > #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL 0x00ff0000 > #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_NEXT_INDEX 0xff000000 > > -/* Compute Express Link (CXL r3.1, sec 8.1.5) */ > +/* Compute Express Link (CXL r3.1, sec 8.1) r3.2 > + * > + * Note that CXL DVSEC id 3 and 7 to be ignored when the CXL link state > + * is "disconnected" (CXL r3.1, sec 9.12.3). Re-enumerate these r3.2 Same sections. :-D With changes: Reviewed-by: Ira Weiny <ira.weiny@intel.com> Ira [snip]
On 3/27/2025 10:11 AM, Ira Weiny wrote: > Terry Bowman wrote: >> CXL and AER drivers need the ability to identify CXL devices. >> >> Add set_pcie_cxl() with logic checking for CXL Flexbus DVSEC presence. The >> CXL Flexbus DVSEC presence is used because it is required for all the CXL >> PCIe devices.[1] >> >> Add boolean 'struct pci_dev::is_cxl' with the purpose to cache the CXL >> Flexbus presence. >> >> Add function pcie_is_cxl() to return 'struct pci_dev::is_cxl'. >> >> [1] CXL 3.1 Spec, 8.1.1 PCIe Designated Vendor-Specific Extended >> Capability (DVSEC) ID Assignment, Table 8-2 >> >> Signed-off-by: Terry Bowman <terry.bowman@amd.com> >> --- >> drivers/pci/pci.c | 5 +++++ >> drivers/pci/probe.c | 10 ++++++++++ >> include/linux/pci.h | 3 +++ >> include/uapi/linux/pci_regs.h | 8 +++++++- >> 4 files changed, 25 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c >> index 869d204a70a3..a1d75f40017e 100644 >> --- a/drivers/pci/pci.c >> +++ b/drivers/pci/pci.c >> @@ -5032,6 +5032,11 @@ static u16 cxl_port_dvsec(struct pci_dev *dev) >> PCI_DVSEC_CXL_PORT); >> } >> >> +inline bool pcie_is_cxl(struct pci_dev *pci_dev) >> +{ >> + return pci_dev->is_cxl; >> +} > Shouldn't this just be a static inline in include/linux/pci.h? Ok, I'll make that change. >> + >> static bool cxl_sbr_masked(struct pci_dev *dev) >> { >> u16 dvsec, reg; > [snip] > >> @@ -741,6 +742,8 @@ static inline bool pci_is_vga(struct pci_dev *pdev) >> return false; >> } >> >> +bool pcie_is_cxl(struct pci_dev *pci_dev); >> + >> #define for_each_pci_bridge(dev, bus) \ >> list_for_each_entry(dev, &bus->devices, bus_list) \ >> if (!pci_is_bridge(dev)) {} else >> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h >> index 3445c4970e4d..7ccb3b2fcc38 100644 >> --- a/include/uapi/linux/pci_regs.h >> +++ b/include/uapi/linux/pci_regs.h >> @@ -1208,9 +1208,15 @@ >> #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL 0x00ff0000 >> #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_NEXT_INDEX 0xff000000 >> >> -/* Compute Express Link (CXL r3.1, sec 8.1.5) */ >> +/* Compute Express Link (CXL r3.1, sec 8.1) > r3.2 > >> + * >> + * Note that CXL DVSEC id 3 and 7 to be ignored when the CXL link state >> + * is "disconnected" (CXL r3.1, sec 9.12.3). Re-enumerate these > r3.2 > Same sections. :-D Got it. I'll change the spec release to 3.2. > With changes: > > Reviewed-by: Ira Weiny <ira.weiny@intel.com> > > Ira > > [snip] Thanks Ira.
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 869d204a70a3..a1d75f40017e 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -5032,6 +5032,11 @@ static u16 cxl_port_dvsec(struct pci_dev *dev) PCI_DVSEC_CXL_PORT); } +inline bool pcie_is_cxl(struct pci_dev *pci_dev) +{ + return pci_dev->is_cxl; +} + static bool cxl_sbr_masked(struct pci_dev *dev) { u16 dvsec, reg; diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index b6536ed599c3..7737b9ce7a83 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1676,6 +1676,14 @@ static void set_pcie_thunderbolt(struct pci_dev *dev) dev->is_thunderbolt = 1; } +static void set_pcie_cxl(struct pci_dev *dev) +{ + u16 dvsec = pci_find_dvsec_capability(dev, PCI_VENDOR_ID_CXL, + PCI_DVSEC_CXL_FLEXBUS); + if (dvsec) + dev->is_cxl = 1; +} + static void set_pcie_untrusted(struct pci_dev *dev) { struct pci_dev *parent = pci_upstream_bridge(dev); @@ -2006,6 +2014,8 @@ int pci_setup_device(struct pci_dev *dev) /* Need to have dev->cfg_size ready */ set_pcie_thunderbolt(dev); + set_pcie_cxl(dev); + set_pcie_untrusted(dev); if (pci_is_pcie(dev)) diff --git a/include/linux/pci.h b/include/linux/pci.h index 47b31ad724fa..af83230bef1a 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -452,6 +452,7 @@ struct pci_dev { unsigned int is_hotplug_bridge:1; unsigned int shpc_managed:1; /* SHPC owned by shpchp */ unsigned int is_thunderbolt:1; /* Thunderbolt controller */ + unsigned int is_cxl:1; /* Compute Express Link (CXL) */ /* * Devices marked being untrusted are the ones that can potentially * execute DMA attacks and similar. They are typically connected @@ -741,6 +742,8 @@ static inline bool pci_is_vga(struct pci_dev *pdev) return false; } +bool pcie_is_cxl(struct pci_dev *pci_dev); + #define for_each_pci_bridge(dev, bus) \ list_for_each_entry(dev, &bus->devices, bus_list) \ if (!pci_is_bridge(dev)) {} else diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 3445c4970e4d..7ccb3b2fcc38 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1208,9 +1208,15 @@ #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL 0x00ff0000 #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_NEXT_INDEX 0xff000000 -/* Compute Express Link (CXL r3.1, sec 8.1.5) */ +/* Compute Express Link (CXL r3.1, sec 8.1) + * + * Note that CXL DVSEC id 3 and 7 to be ignored when the CXL link state + * is "disconnected" (CXL r3.1, sec 9.12.3). Re-enumerate these + * registers on downstream link-up events. + */ #define PCI_DVSEC_CXL_PORT 3 #define PCI_DVSEC_CXL_PORT_CTL 0x0c #define PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR 0x00000001 +#define PCI_DVSEC_CXL_FLEXBUS 7 #endif /* LINUX_PCI_REGS_H */
CXL and AER drivers need the ability to identify CXL devices. Add set_pcie_cxl() with logic checking for CXL Flexbus DVSEC presence. The CXL Flexbus DVSEC presence is used because it is required for all the CXL PCIe devices.[1] Add boolean 'struct pci_dev::is_cxl' with the purpose to cache the CXL Flexbus presence. Add function pcie_is_cxl() to return 'struct pci_dev::is_cxl'. [1] CXL 3.1 Spec, 8.1.1 PCIe Designated Vendor-Specific Extended Capability (DVSEC) ID Assignment, Table 8-2 Signed-off-by: Terry Bowman <terry.bowman@amd.com> --- drivers/pci/pci.c | 5 +++++ drivers/pci/probe.c | 10 ++++++++++ include/linux/pci.h | 3 +++ include/uapi/linux/pci_regs.h | 8 +++++++- 4 files changed, 25 insertions(+), 1 deletion(-)