| Message ID | 20250317054151.6095-4-quic_pkumpatl@quicinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Enable audio on qcs6490-RB3Gen2 and qcm6490-idp boards | expand |
On 3/17/25 6:41 AM, Prasad Kumpatla wrote: > From: Mohammad Rafi Shaik <quic_mohs@quicinc.com> > > Modify and enable WSA, VA and lpass_tlmm clock properties. > For audioreach solution mclk, npl and fsgen clocks > are enabled through the q6prm clock driver. > > Signed-off-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com> > Co-developed-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com> > Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com> > --- Instead, put the inverse changes in sc7280-chrome-common.dtsi please Konrad
Hi Konrad, On Tue Apr 1, 2025 at 6:05 PM CEST, Konrad Dybcio wrote: > On 3/17/25 6:41 AM, Prasad Kumpatla wrote: >> From: Mohammad Rafi Shaik <quic_mohs@quicinc.com> >> >> Modify and enable WSA, VA and lpass_tlmm clock properties. >> For audioreach solution mclk, npl and fsgen clocks >> are enabled through the q6prm clock driver. >> >> Signed-off-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com> >> Co-developed-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com> >> Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com> >> --- > > Instead, put the inverse changes in sc7280-chrome-common.dtsi please How are we going to handle other sc7280-based platforms, such as my QCM6490 Fairphone 5 needing to use q6afecc instead of q6prmcc which gets used in this patchset? One solution might be to put q6afecc into the base sc7280.dtsi file, then we have a sc7280-audioreach.dtsi which overwrites q6afecc with q6prmcc which then gets included by boards using audioreach. I also don't think we can split this across sc7280 vs qcm6490 vs sm7325, there seems to be any combination possible on any of these SoCs - depending on the firmware shipped with it. So somewhat similar to the current sc7280-chrome-common.dtsi but just for audioreach. Regards Luca > > Konrad
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 7a36c90ad4ec..23dea375c213 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -12,6 +12,7 @@ #include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include <dt-bindings/sound/qcom,q6afe.h> #include "sc7280.dtsi" #include "pm7250b.dtsi" #include "pm7325.dtsi" @@ -666,6 +667,36 @@ redriver_usb_con_sbu: endpoint { }; }; +&lpass_tlmm { + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; +}; + +&lpass_va_macro { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + clocks = <&q6prmcc LPASS_CLK_ID_VA_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "mclk", "macro", "dcodec"; + + status = "okay"; +}; + +&lpass_wsa_macro { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_va_macro>; + clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; + + status = "okay"; +}; + &mdss { status = "okay"; };