| Message ID | 20250410005912.118732-6-aford173@gmail.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [1/9] arm64: dts: imx8mm-beacon: Fix RTC capacitive load | expand |
On Wed, Apr 09, 2025 at 07:59:00PM -0500, Adam Ford wrote: > The ethernet PHY setup assumes the bootloader will pull the PHY out > of reset,but it's not guaranteed. The PHY is also currently Need space after, > setup to poll, because it does not configure the IRQ. Enable > both GPIO settings for better optimal ethernet performance. suggested commit message arm64: dts: imx8mm-beacon: Configure Ethernet PHY reset and GPIO IRQ The Ethernet PHY setup currently assumes that the bootloader will take the PHY out of reset, but this behavior is not guaranteed across all bootloaders. Add the reset GPIO to ensure the kernel can properly control the PHY reset line. Also configure the PHY IRQ GPIO to enable interrupt-driven link status reporting, instead of relying on polling. This ensures more reliable Ethernet initialization and improves PHY event handling. Frank > > Signed-off-by: Adam Ford <aford173@gmail.com> > --- > arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi > index 9ba0cb89fa24..ed7a1be4a1a6 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi > @@ -78,6 +78,9 @@ mdio { > ethphy0: ethernet-phy@0 { > compatible = "ethernet-phy-ieee802.3-c22"; > reg = <0>; > + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; > + interrupt-parent = <&gpio1>; > + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; > }; > }; > }; > @@ -315,6 +318,7 @@ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f > MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 > MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 > MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f > + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146 > MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 > >; > }; > -- > 2.48.1 >
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index 9ba0cb89fa24..ed7a1be4a1a6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -78,6 +78,9 @@ mdio { ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; }; }; }; @@ -315,6 +318,7 @@ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 >; };
The ethernet PHY setup assumes the bootloader will pull the PHY out of reset,but it's not guaranteed. The PHY is also currently setup to poll, because it does not configure the IRQ. Enable both GPIO settings for better optimal ethernet performance. Signed-off-by: Adam Ford <aford173@gmail.com> --- arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | 4 ++++ 1 file changed, 4 insertions(+)